TSV Decoupling Capacitor Reduces Inductance in 3D Stacked Chips
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Solution Overview
Problem
In three-dimensional silicon (3DSi) structures, the increasing circuit density and switching activity lead to noise generation issues due to high inductance between active circuits and decoupling capacitors, requiring more capacitors to control noise, which complicates power distribution and impacts device performance.
Innovation Solution
A decoupling capacitor design using a conductive through-substrate via (TSV) as an inner electrode and a columnar doped semiconductor region as an outer electrode, providing low inductance and high decoupling capacitance in a small area, with additional TSVs for power and signal transmission, reducing high-frequency noise in stacked semiconductor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If deep trench capacitors are embedded within active silicon devices to control noise, then noise control capability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from planar trench capacitors to three-dimensional stacked capacitor structures. Multiple capacitor plates are stacked vertically with dielectric layers between them, utilizing the vertical dimension to increase capacitance density. This dimensional change allows achieving the required noise control capability without increasing lateral device complexity or requiring extensive trench arrays within active silicon regions.
Solution Approach 2:
The capacitor structure serves multiple functions: it provides decoupling capacitance for noise control, acts as an integrated power distribution element, and can be formed using standard semiconductor processing techniques that are compatible with existing device fabrication. The stacked capacitor design can be implemented alongside other device structures without requiring separate dedicated noise control regions.
2Object-affected harmful factors
If a large array of deep trench capacitors is required to obtain sufficient decoupling, then noise control capability is improved, but inductance between active circuits and capacitors increases
Solution Approach 1:
By stacking capacitor plates vertically in three dimensions, the patent reduces the lateral footprint required for achieving sufficient decoupling capacitance. This vertical integration places the capacitance closer to the active circuits in the vertical dimension, reducing the loop area and associated inductance compared to spreading out a large array of trench capacitors laterally.
Solution Approach 2:
The stacked capacitor structure nests multiple capacitor plates within a compact vertical space, with each plate surrounded by dielectric and conductive layers. This nested configuration concentrates the capacitance in a localized region near the active circuits, minimizing the current loop area and reducing inductance while achieving the required decoupling effect.
3Productivity
If circuit density is increased in three-dimensional silicon structures, then productivity and integration are improved, but noise generation increases
Solution Approach 1:
The patent implements localized stacked capacitor structures positioned near specific high-switching-activity circuit regions. By placing decoupling capacitance locally at the site of noise generation rather than using distant large arrays, the solution addresses noise from high-density circuits without requiring additional lateral space that would reduce overall circuit density.
Solution Approach 2:
The vertical stacking of capacitors provides sufficient decoupling capacitance in a compact footprint, allowing high circuit density to be maintained in the lateral plane. The three-dimensional capacitor structure delivers the required noise control capability without consuming additional lateral space that would otherwise be available for active circuits.
4Object-affected harmful factors
If more decoupling capacitors are added to control noise in high-density circuits, then noise control capability is improved, but the area occupied by capacitor structures increases
Solution Approach 1:
The stacked capacitor design utilizes the vertical dimension to achieve high capacitance values within a minimal lateral footprint. Multiple capacitor plates are stacked one above another with thin dielectric layers, concentrating the capacitance function in the vertical direction and freeing up lateral area for additional active circuits while maintaining adequate noise control capability.
Solution Approach 2:
The patent changes the geometric parameters of the capacitor structure by transitioning from shallow planar trenches to deep vertical stacks. This parameter change increases the effective capacitance per unit lateral area by utilizing the vertical dimension, thereby achieving the required noise control capability with significantly reduced footprint compared to conventional trench capacitor arrays.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The capacitor design effectively reduces high-frequency noise in power supply systems by minimizing inductance, allowing for more efficient noise control without increasing circuit density or altering the 3DSi structural design, thereby enhancing device performance.
Implementation Method 1
The inner electrode includes a conductive through-substrate via (TSV) structure that contiguously extends at least from an upper surface of the semiconductor substrate to a lower surface of the semiconductor substrate
Implementation Method 2
a columnar doped semiconductor region as an outer electrode. The capacitor provides a large decoupling capacitance in a small area
Data Source
AI summary
A capacitor in a semiconductor substrate employs a conductive through-substrate via (TSV) as an inner electrode and a columnar doped semiconductor region as an outer electrode. The capacitor provides a large decoupling capacitance in a small area, and does not impact circuit density or a Si3D structural design. Additional conductive TSV's can be provided in the semiconductor substrate to provide electrical connection for power supplies and signal transmission therethrough. The capacitor has a lower inductance than a conventional array of capacitors having comparable capacitance, thereby enabling reduction of high frequency noise in the power supply system of stacked semiconductor chips.