TSV Parasitic Capacitance Reduction via Deep Trench Isolation
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Solution Overview
Problem
In integrated circuit technology, the use of n+ epitaxy layers with through-silicon vias (TSVs) leads to significant parasitic capacitance and voltage and frequency dependence, complicating device modeling in eDRAM applications.
Innovation Solution
The implementation of a deep trench isolation structure or a grounded through-silicon via surrounding the TSV conductor, along with a p-doped region of higher dopant concentration, electrically isolates the epitaxy layer from signal voltages, preventing capacitance from entering the inversion mode and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an n+ epitaxy layer is used in eDRAM technology with TSVs, then the device structure is formed, but parasitic capacitance significantly increases and voltage/frequency dependence complicates modeling
Solution Approach 1:
An intrinsic or lightly-doped semiconductor layer is introduced as an intermediary between the n+ epitaxy layer and the TSV conductor. This intermediate layer acts as a buffer that prevents direct capacitive coupling between the conductive TSV and the heavily doped n+ epitaxy, thereby reducing parasitic capacitance while maintaining the structural integrity of the eDRAM device
Solution Approach 2:
The patent applies local quality by creating a region with different doping characteristics (intrinsic or lightly-doped) specifically at the interface between the TSV and the n+ epitaxy layer. This localized modification of material properties reduces parasitic capacitance in the critical region without affecting the overall device structure or performance
2Ease of operation
If voltage is applied to the TSV conductor in the presence of an n+ epitaxy layer, then the device operates, but capacitance enters inversion mode introducing voltage and frequency dependence
Solution Approach 1:
The patent changes the doping parameter of the epitaxy layer from heavily doped (n+) to intrinsic or lightly-doped in the region adjacent to the TSV. This parameter change ensures that the capacitance remains in depletion mode rather than transitioning to inversion mode under operating voltages, thereby eliminating voltage and frequency dependence and simplifying the capacitance model
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, stabilizes TSV operation in the depletion mode, and simplifies modeling by eliminating voltage and frequency dependency, allowing for the use of n+ epitaxy layers in eDRAM technology without increased capacitance issues.
Implementation Method 1
A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device
Implementation Method 2
A trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench
Data Source
AI summary
A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance.