Memory Core Chip TSV Defect Rerouting via Domino Switch
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Solution Overview
Problem
It is challenging to diagnose and isolate defects in signal paths within semiconductor chips before they are stacked, as it is difficult to determine whether the issue lies with the TSVs or their connections, leading to inefficient defect detection and recovery.
Innovation Solution
The implementation of a domino switch circuit and latch circuits that allow for fail information to be stored and used to switch between signal paths, enabling the use of spare paths to bypass defective ones without replacing individual TSVs, and allowing for testing of input/output circuits before chip stacking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSVs are used to penetrate through semiconductor substrates to form signal paths, then connectivity between stacked chips is improved, but defect detection and isolation become difficult after stacking
Solution Approach 1:
The patent implements preliminary defect detection by providing test circuits on the same semiconductor substrate as the TSVs, allowing signal paths to be tested before chip stacking. This preliminary action enables identification of defective TSVs or connection points prior to assembly, preventing defective units from being stacked and eliminating the difficulty of post-stack defect isolation.
2Reliability
If spare signal paths are used to replace defective paths, then system reliability is recovered, but defect location identification remains challenging
Solution Approach 1:
The patent implements feedback mechanisms through test circuits that provide information about the conduction state of each TSV and signal path. This feedback enables identification of defective locations before stacking, allowing precise isolation and replacement of only the defective TSVs or connection points while maintaining information about defect locations.
3Ease of manufacture
If input/output circuits are tested only after chip stacking, then manufacturing process is simplified, but testing efficiency and defect isolation are reduced
Solution Approach 1:
The patent merges the test circuits with the input/output circuits on the same semiconductor substrate, integrating testing functionality directly into the chip structure. This merging allows testing to be performed at the wafer level before dicing and stacking, maintaining manufacturing simplicity while dramatically improving testing efficiency and enabling defect isolation at the individual TSV level.
Data Source
AI summary
Disclosed herein is an apparatus that includes a memory cell array, a plurality of TSVs penetrating a semiconductor chip, an output circuit configured to output a data to the TSVs, an input circuit configured to receive a data from the TSVs, a pad supplied with a data from outside, and a control circuit configured to write the data to the memory cell array, read the data from the memory cell array, and transfer the data from the memory cell array to the input circuit via the output circuit and the TSVs.