TSV Die Embedding in Encapsulant with Conductive TMV for Vertical Interconnect
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving a cost-effective and efficient vertical electrical interconnect for semiconductor package-on-package (PoP) configurations, leading to larger package sizes and increased manufacturing costs due to the large form factor of traditional conductive through hole vias (THVs) and through silicon vias (TSVs).
Innovation Solution
A method involving the embedding of a TSV semiconductor die within an encapsulant with a conductive through mold via (TMV) is developed, which includes forming a conductive layer, mounting semiconductor dies, depositing an encapsulant, forming conductive vias through the encapsulant, and creating interconnect structures to enable vertical interconnects with a smaller form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional conductive through hole vias (THVs) or through silicon vias (TSVs) are used for vertical interconnect, then electrical connection is achieved, but the package size becomes large and manufacturing cost increases
Solution Approach 1:
The patent divides the vertical interconnect structure into multiple segments: THVs/TSVs are formed only in the encapsulant or substrate, not through the entire stack. The interconnect is segmented across multiple layers with intermediate conductive layers and insulating layers, allowing electrical connection without requiring a single large via structure, thus reducing package footprint.
Solution Approach 2:
The patent transitions from traditional planar interconnect to three-dimensional stacked architecture. Multiple semiconductor dies are stacked vertically with THVs/TSVs providing inter-layer connections. This vertical stacking in the z-dimension reduces the horizontal footprint while maintaining electrical interconnect functionality.
2Reliability
If traditional THVs or TSVs are used for vertical interconnect, then electrical connection is achieved, but manufacturing cost increases
Solution Approach 1:
The manufacturing process is segmented into discrete steps: forming THVs/TSVs in encapsulant/substrate, depositing conductive layers, forming insulating layers, and stacking dies. This segmentation allows each step to be optimized independently and enables parallel processing, reducing overall manufacturing complexity and cost compared to forming single large through-vias.
Solution Approach 2:
THVs and TSVs are formed preliminarily in the encapsulant and substrate before die stacking. Conductive and insulating layers are deposited in advance. This preliminary preparation simplifies the subsequent assembly process and enables higher throughput manufacturing, reducing costs.
3Ease of manufacture
If larger package size is used for traditional vertical interconnect, then manufacturing is simpler, but unit density on substrate decreases
Solution Approach 1:
The patent moves manufacturing complexity to the vertical dimension through multi-layer stacking. Multiple thin layers of conductive and insulating materials are deposited alternately, with each layer being simple to manufacture. The high unit density is achieved by stacking many such simple layers vertically rather than creating complex large-area structures horizontally.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a smaller semiconductor package footprint, higher unit density on a substrate, and reduced manufacturing costs by simplifying the assembly process and enhancing productivity while maintaining high yield and design flexibility.
Implementation Method 1
depositing an encapsulant around the first semiconductor die and over the first conductive layer to embed the first semiconductor die
Implementation Method 2
forming a conductive TMV through the encapsulant
Data Source
AI summary
A semiconductor device has a carrier or first conductive layer with a plurality of TSV semiconductor die mounted over the carrier or first conductive layer. An encapsulant is deposited around the first semiconductor die and over the carrier or first conductive layer to embed the first semiconductor die. A conductive TMV is formed through the encapsulant. A second conductive layer is formed over a first surface of the encapsulant. A first insulating layer is formed over the first surface of the encapsulant while exposing portions of the second conductive layer. A second insulating layer is formed over the second surface of the encapsulant while exposing portions of the first conductive layer. Alternatively, a first interconnect structure is formed over the first surface of the encapsulant. The carrier is removed and a second interconnect structure is formed over a second surface of the encapsulant.