Dielectric Liner Integration for TSV Manufacturing
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Solution Overview
Problem
Conventional semiconductor device manufacturing processes for through-substrate vias (TSVs) are complex and require multiple steps, including a spacer CMP process to remove dielectric liner material, which can damage underlying structures and necessitate thick underlying dielectric material and additional dielectric deposition, increasing process complexity.
Innovation Solution
The method eliminates the spacer CMP step by incorporating the outer portion of the dielectric liner material into the final device, using it as part of the damascene dielectric material, allowing for a thinner underlying dielectric and reducing the need for additional dielectric deposition, thereby simplifying the process and protecting underlying structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a continuous dielectric liner material layer is deposited over the front-side of the wafer and into the openings, then the dielectric liner can be formed, but the process requires an additional spacer CMP step to remove excess material which increases process complexity
Solution Approach 1:
The patent extracts and eliminates the spacer CMP step from the conventional process by using a dielectric liner material with inherently different etch rates that allow selective removal of excess material during the TSV etch-back process, thereby simplifying the overall manufacturing process while maintaining precise dielectric liner formation
Solution Approach 2:
The patent changes the etch rate parameter of the dielectric liner material relative to surrounding materials, enabling selective removal of excess dielectric liner material during TSV etch-back without requiring a separate spacer CMP process step
2Manufacturing precision
If the dielectric liner material on the outer surface of the wafer is removed using spacer CMP, then the top portion of continuous dielectric liner material can be removed, but underlying structures can be damaged
Solution Approach 1:
The patent changes the etch selectivity parameter by using a dielectric liner material with significantly different etch rate characteristics compared to underlying structures, allowing selective removal of excess material during TSV etch-back while protecting underlying structures from damage
Solution Approach 2:
The patent uses the etch rate difference as an intermediary mechanism to selectively remove excess dielectric liner material while the TSV conductive fill material acts as a protective intermediary layer that prevents damage to underlying structures during the removal process
3Manufacturing precision
If conventional TSV manufacturing processes are used, then through-substrate vias can be formed, but several process steps and materials increase manufacturing complexity
Solution Approach 1:
The patent merges the dielectric liner formation process with the TSV etch-back process by utilizing etch rate differences, combining what were previously separate steps (dielectric liner deposition and excess material removal) into a more integrated process flow that reduces overall manufacturing complexity
Solution Approach 2:
The patent gives the dielectric liner material multiple functions: it provides electrical isolation, serves as an etch stop layer, and enables selective material removal during TSV etch-back, thereby reducing the need for additional dedicated process steps and materials
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of process steps and materials needed, minimizes damage to underlying structures, and enhances manufacturing efficiency by using the dielectric liner material as a protective layer during subsequent CMP processes.
Implementation Method 1
deposited in a continuous, conformal manner (e.g., by physical vapor deposition (PVD) or chemical vapor deposition (CVD))
Implementation Method 2
deposited in a continuous, conformal manner (e.g., by physical vapor deposition (PVD) or chemical vapor deposition (CVD))
Implementation Method 3
the dielectric liner material on the outer surface of the wafer is removed using a chemical-mechanical planarization process with a suitable slurry ('spacer CMP')
Data Source
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AI summary
Methods of manufacturing semiconductor devices and semiconductor devices with through-substrate vias (TSVs). One embodiment of a method of manufacturing a semiconductor device includes forming an opening through a dielectric structure and at least a portion of a semiconductor substrate, and forming a dielectric liner material having a first portion lining the opening and a second portion on an outer surface of the dielectric structure laterally outside of the opening. The method further includes removing the conductive material such that the second portion of the dielectric liner material is exposed, and forming a damascene conductive line in the second portion of the dielectric liner material that is electrically coupled to the TSV.