Through-Silicon Via Fabrication via Differential Polishing

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The challenge in fabricating through-silicon via structures is maintaining the depth of the interlayer dielectric layer during the polishing process, as the chemical mechanical polishing process struggles to differentiate between the interlayer dielectric layer and the dielectric layer for the through-silicon via, leading to excessive loss of the interlayer dielectric layer.

Innovation Solution

A method involving forming a semiconductor substrate with a semiconductor device, depositing a dielectric layer, creating via holes, filling them with a conductive layer, performing etching and planarizing processes, and using a conductive layer with a different removal rate under the same slurry to stop the polishing process at the interlayer dielectric layer, thereby preventing its loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If chemical mechanical polishing process is used to form contact plugs and through-silicon via electrode, then the polishing process can remove material layers, but the interlayer dielectric layer depth becomes difficult to control due to excessive loss during polishing

Engineering Contradiction:

Improveinterlayer dielectric layer depth controlVSAvoidinterlayer dielectric layer loss

Core Design Contradiction:

Manufacturing precisionVSLoss of substance

Solution Approach 1:

A planarization layer is formed over the interlayer dielectric layer before the chemical mechanical polishing process. This preliminary action provides a sacrificial layer that protects the interlayer dielectric layer from excessive polishing, allowing the polishing process to stop at the desired depth without compromising the underlying dielectric layer.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The planarization layer acts as an intermediary between the polishing process and the interlayer dielectric layer. It absorbs the polishing action and prevents direct contact between the polishing slurry and the interlayer dielectric layer, thereby preventing material loss while still allowing the polishing process to proceed.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of manufacture

If the interlayer dielectric layer and dielectric layer for isolating through-silicon via both have same removal rate under the same slurry, then the polishing process cannot differentiate between layers, but this causes difficulty in stopping the polishing on either layer

Engineering Contradiction:

Improvepolishing process simplicityVSAvoidlayer depth control

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The planarization layer serves as an intermediary that enables the polishing process to differentiate between layers. By having a distinct layer with different polishing characteristics on top of the interlayer dielectric layer, the polishing process can be controlled to stop at the desired depth without directly polishing the underlying dielectric layers.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The structure is segmented into multiple layers with different polishing characteristics. The planarization layer is separated from the interlayer dielectric layer, allowing independent control of their polishing rates. This segmentation enables precise depth control during the chemical mechanical polishing process.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively maintains the depth of the interlayer dielectric layer, ensuring precise control and preventing its loss during the polishing process, which enhances the fabrication of through-silicon via structures and improves the performance of 3D stack ICs by maintaining the structural integrity and electrical connectivity.

Implementation Method 1

A plurality of chemical mechanical polishing processes are conducted to form the aforementioned contact plugs and through-silicon via electrode

Methodology Applied

Scientific EffectChemical mechanical polishing:

Implementation Method 2

performing a first planarizing process to remove a portion of the second conductive layer

Methodology Applied

Scientific EffectAbrasion: Abrasion

Implementation Method 3

performing an etching process to form a through-silicon via in the first conductive layer, the dielectric layer, and the semiconductor substrate

Methodology Applied

Scientific EffectEtching:

Data Source

PatentUS8202766B2Method for fabricating through-silicon via structure

Publication Date: 2012.06.19 UNITED MICROELECTRONICS CORP

AI summary

A method for fabricating through-silicon via structure includes the steps of: providing a semiconductor substrate; forming at least one semiconductor device on surface of the semiconductor substrate; forming a dielectric layer on the semiconductor device, in which the dielectric layer includes at least one via hole; forming a first conductive layer on the dielectric layer and filling the via hole; performing an etching process to form a through-silicon via in the first conductive layer, the dielectric layer, and the semiconductor substrate; depositing a second conductive layer in the through-silicon via and partially on the first conductive layer; and planarizing a portion of the second conductive layer until reaching the surface of the first conductive layer.