Through Silicon Via Packaging with Direct Interconnects
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Solution Overview
Problem
Current integrated circuit packaging technologies face challenges in accommodating high-speed devices, particularly in reducing size, increasing reliability, addressing thermal and EMI issues, and achieving cost-effectiveness, while also dealing with complexity and error risks in manufacturing.
Innovation Solution
The implementation of a through silicon via die with a re-distribution layer and direct interconnects, which includes mounting a structure over the die, connecting it with direct interconnects, and encapsulating the die and structure, to create a robust and compact packaging system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional packaging technologies are used, then manufacturing processes are simpler, but package size is larger and frequency transmission is lower
Solution Approach 1:
The patent segments the packaging system into distinct functional layers: through-silicon via die, re-distribution layer, mounted structure, direct interconnects, and encapsulation. This segmentation allows each component to be optimized independently for size and performance while managing manufacturing complexity through modular assembly processes.
Solution Approach 2:
The patent transitions from planar interconnect architectures to three-dimensional vertical stacking with through-silicon vias and direct interconnects. This dimensional change enables higher frequency transmission and smaller package footprint by utilizing the vertical dimension for signal routing and component placement.
2Area of moving object
If package size is reduced, then integration density increases, but thermal management becomes more difficult
Solution Approach 1:
The patent implements nested packaging where multiple functional structures are stacked vertically within a compact footprint. The through-silicon via die, re-distribution layer, and mounted structure are nested in layers, enabling high integration density while maintaining thermal pathways through the vertical architecture.
Solution Approach 2:
The re-distribution layer acts as an intermediary between the through-silicon via die and the mounted structure, providing both electrical interconnection and thermal management pathways. This intermediary layer facilitates heat dissipation while enabling compact vertical integration.
3Speed
If direct interconnects are used, then frequency transmission increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary alignment features and pre-formed interconnect structures in the through-silicon via die and re-distribution layer. These preliminary preparations establish precise registration marks and alignment references that guide subsequent mounting operations, enabling high-frequency direct interconnects while managing manufacturing precision requirements.
Solution Approach 2:
The patent replaces traditional mechanical alignment and bonding processes with direct interconnect architectures that utilize self-alignment features and integrated connection structures. This substitution reduces the need for high-precision mechanical alignment while enabling higher frequency transmission through direct electrical pathways.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: providing a through silicon via die having an interconnect through a silicon substrate; depositing a re-distribution layer on the through silicon via die and connected to the interconnects; mounting a structure over the through silicon via die; connecting the structure to the interconnect of the through silicon via die with a direct interconnect; and encapsulating the through silicon via die and partially encapsulating the structure with an encapsulation.