Through Silicon Vias on Double Sided Interconnect Devices
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Solution Overview
Problem
Current semiconductor technologies face challenges in integrating high-performance and low-capacitance, low-power devices within a single die or chip, particularly in achieving efficient electrical connections across both sides of a device stratum for enhanced performance and capacity.
Innovation Solution
The implementation of through silicon vias (TSVs) connected to interconnect levels on both sides of a device stratum, allowing for direct electrical and physical connections between the TSVs and the device stratum, enabling efficient power and control interconnects while minimizing semiconductor layer consumption and eliminating the need for additional redistribution layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional single-sided interconnect structures are used, then device layout is simple, but electrical connection efficiency between both sides of device stratum is poor
Solution Approach 1:
The patent transitions from single-sided planar interconnects to double-sided three-dimensional interconnects by forming through-silicon vias that penetrate the substrate. This dimensional change enables direct electrical connections between interconnect levels on opposite sides of the device stratum, dramatically improving connection efficiency and reducing signal path length without simply extending planar traces.
Solution Approach 2:
The interconnect structure is segmented into multiple independent conductive layers on each side of the device stratum (first interconnect levels and second interconnect levels). These segmented layers are electrically isolated from each other except through the controlled TSV connections, allowing independent routing and reducing parasitic coupling while maintaining high connection efficiency.
2Reliability
If additional redistribution layers are added to achieve bilateral connections, then electrical connection efficiency improves, but semiconductor area usage increases
Solution Approach 1:
Instead of adding more planar redistribution layers that consume horizontal area, the patent utilizes the vertical dimension by forming TSVs that pass through the substrate. This allows direct point-to-point connections between opposing sides, achieving efficient bilateral interconnection without increasing the chip footprint.
Solution Approach 2:
The TSV connections are formed locally at specific positions where interconnect levels on opposite sides need to be joined. Rather than adding global redistribution layers across the entire chip area, connections are established only where needed, minimizing area consumption while maintaining high connection efficiency at critical locations.
3Adaptability or versatility
If more semiconductor layers are used for bilateral interconnects, then connection capability improves, but device density decreases
Solution Approach 1:
The patent achieves enhanced bilateral connection capability by exploiting the vertical dimension through TSV formation rather than adding more horizontal layers. The TSVs provide direct through-substrate pathways that enable sophisticated bilateral interconnect patterns without consuming additional lateral space, thereby maintaining high device density while improving connection versatility.
Solution Approach 2:
The TSV structure serves multiple functions simultaneously: it provides electrical connection between interconnect levels on opposite sides, acts as a via for signal routing, and enables flexible bilateral interconnect patterns. This multi-functionality achieves high adaptability for various connection scenarios without requiring separate dedicated structures for each function, preserving device density.
Data Source
AI summary
An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more interconnect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.