3D Stacked DRAM with TSVs for Capacitor Reliability
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Solution Overview
Problem
As semiconductor process sizes decrease, the reduced size of DRAM storage capacitors leads to reduced capacitance and increased charge loss, compromising memory cell reliability, especially under high temperature conditions.
Innovation Solution
The implementation of a 3D IC structure in DRAM apparatus, where memory cells and storage capacitors are connected through-silicon vias (TSVs), allowing for independent placement and sizing of storage capacitors without area constraints, enhancing efficiency and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the minimum size of the semiconductor process is reduced, then the chip size of the DRAM is reduced, but the area of the storage capacitor is reduced leading to reduced capacitance and reliability
Solution Approach 1:
The patent transitions from a planar 2D arrangement to a 3D stacked architecture where memory cells and storage capacitors are distributed across multiple layers. This dimensional change allows the storage capacitors to be placed in separate layers from memory cells, enabling larger capacitor areas without increasing the footprint of the memory cell array, thus maintaining reliability while reducing overall chip size.
Solution Approach 2:
The patent divides the DRAM structure into separate functional modules: memory cell arrays in one layer and storage capacitors in another layer. This segmentation allows independent optimization of each component - memory cells can be densely packed in the array layer while storage capacitors can be sized appropriately in the capacitor layer, resolving the contradiction between miniaturization and reliability.
2Area of stationary object
If the area of the storage capacitor is reduced, then the chip size is reduced, but the capacitance provided by the storage capacitor is reduced
Solution Approach 1:
By moving storage capacitors to a separate layer in the 3D stack, the patent enables storage capacitors to occupy vertical space rather than horizontal space. This allows the memory cell array to maintain a compact footprint while storage capacitors can be sized to provide adequate capacitance in the capacitor layer, decoupling the area-capacitance relationship.
3Ease of manufacture
If high temperature processing is applied to reduce the size of the storage capacitor, then the manufacturing process is simplified, but charge loss of the storage capacitor is increased
Solution Approach 1:
The patent separates storage capacitors from memory cells into different layers, allowing storage capacitors to be formed using standard high-temperature processes without directly impacting memory cell performance. The spatial separation means that even if storage capacitors experience some charge loss during high-temperature processing, the memory cell operation is not compromised, as they are electrically isolated.
4Device complexity
If storage capacitors are integrated within the same chip as memory cells, then the device structure is simplified, but the area of storage capacitors is constrained
Solution Approach 1:
The patent uses 3D stacking to distribute storage capacitors and memory cells across different vertical layers. This dimensional arrangement allows both components to coexist in a compact footprint while each having sufficient area - memory cells in the array layer and storage capacitors in the capacitor layer, connected via vertical interconnects.
Solution Approach 2:
The patent implements a nested structure where storage capacitors are placed in separate layers beneath or above the memory cell array. This nesting approach allows the storage capacitor area to be independently optimized without consuming horizontal space in the memory cell array, effectively allowing larger capacitors within the same overall chip footprint.
Data Source
AI summary
The present invention provides a dynamic random access memory apparatus includes a first chip and a second chip. The first chip includes a plurality of memory cells and a plurality of through-silicon vias (TSVs). The plurality of memory cells are arranged in an array. First terminals of the TSVs are respectively coupled to the memory cells. The first chip and the second chip are overlapped, the second chip includes a plurality storage capacitors. Second terminals of the TSVs are respectively coupled to the storage capacitors storage capacitors.