TSV-Based Off-Chip Driver Pin Capacitance Reduction
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Solution Overview
Problem
In vertically stacked semiconductor memory die configurations, pin capacitance increases with the number of die, limiting the maximum number of stacked die due to the dominance of off-chip driver sizing, which affects switching times and power consumption.
Innovation Solution
Through-silicon vias (TSVs) connect internal nodes of off-chip drivers between selected and unselected die, reducing off-chip driver sizing and pin capacitance, while adjustable delay lines synchronize input signal timing to minimize crowbar current and optimize driver performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If vertically stacked semiconductor memory die configurations are used to reduce form factor and package size, then the number of stacked die increases, but pin capacitance increases which limits the maximum number of stacked die
Solution Approach 1:
The patent divides the off-chip driver functionality into multiple segments across different die. Each die has its own off-chip driver that can be independently controlled, allowing the total pin capacitance to be distributed and managed across multiple smaller units rather than one large driver on a single die.
Solution Approach 2:
The patent implements dynamic control of off-chip drivers where drivers on unselected die can be disabled or put into high-impedance state. This dynamic switching allows the system to adapt the active driver configuration based on which die is currently selected, effectively reducing the active pin capacitance at any given time.
2Quantity of substance
If off-chip driver sizing is increased to handle higher pin capacitance, then more die can be stacked, but switching times increase and power consumption increases
Solution Approach 1:
By segmenting the driver functionality across multiple die, each driver handles a smaller portion of the total capacitance load. This allows for more efficient switching operations and reduced power consumption per driver, while collectively supporting a larger number of stacked die.
Solution Approach 2:
The dynamic enabling/disabling of off-chip drivers on unselected die ensures that only the necessary drivers are active at any given time. This reduces the total power consumption and improves switching times by avoiding the need to drive unnecessary capacitive loads.
Data Source
AI summary
Methods for reducing pin capacitance and improving off-chip driver performance by using TSVs to enable usage of off-chip drivers located within selected and unselected die of a plurality of stacked die are described. A reduction in pin capacitance allows for faster switching times and/or lower power operation. In some embodiments, a TSV may connect an internal node (e.g., the output of a pre-driver) within a selected die of a plurality of stacked die with the input of an off-chip driver within an unselected die of the plurality of stacked die. In some cases, only a single die within a die stack may be selected (or enabled) at a given time. Using a TSV to connect internal nodes associated with off-chip drivers located within both selected and unselected die of the die stack allows for reduced off-chip driver sizing and thus reduced pin capacitance.