TSV Layout Isolation With Dummy Devices for Stress Uniformity

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Solution Overview

Problem

The implementation of through-substrate vias (TSVs) in 3DICs causes stress on active regions, affecting the performance of nearby devices due to fabrication process stresses and thermal expansion mismatches, leading to non-uniform loading effects.

Innovation Solution

A keep-out-zone (KOZ) is established around TSVs to restrict active device placement, with dummy devices placed within this zone to ensure uniform distribution and reduce stress impacts, and the dimensions of dummy active regions are standardized to enhance uniformity and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If through-substrate vias (TSVs) are implemented to form 3DIC, then integration density is improved, but stress on active regions increases affecting device performance

Engineering Contradiction:
Improveintegration densityVSAvoiddevice performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The substrate is divided into a first region containing TSVs and a second region containing active devices, with an isolation region separating them. This spatial segmentation prevents stress from TSVs from affecting active devices while maintaining high integration density through die stacking.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the substrate are assigned different functions: the first region accommodates TSVs for vertical interconnection, the isolation region provides stress relief, and the second region hosts active devices. This local differentiation optimizes both integration density and device performance.

Inventive Principle:
Principle #3Local quality

2Device complexity

If TSVs are formed to enable die stacking, then 3DIC capability is achieved, but non-uniform loading effects occur on active regions

Engineering Contradiction:
Improve3DIC capabilityVSAvoidloading uniformity
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

An isolation region acts as an intermediary between TSVs and active devices, absorbing and distributing mechanical stress to prevent non-uniform loading effects on active regions while enabling 3DIC stacking capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Area of stationary object

If active devices are placed near TSVs to maximize area utilization, then area efficiency is improved, but stress impact on devices increases

Engineering Contradiction:
Improvearea utilizationVSAvoidstress impact
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The physical parameters of the isolation region (width, material composition, depth) are optimized to provide sufficient stress isolation while minimizing area consumption, balancing area utilization with stress protection for active devices.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11748544B2Method of manufacturing integrated circuit having through-substrate via
Publication Date: 2023.09.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11748544B2 patent drawing
  • US11748544B2 patent drawing
  • US11748544B2 patent drawing

AI summary

A method includes generating an integrated circuit (IC) layout design and manufacturing an IC based on the IC layout design. Generating the IC layout design includes generating a pattern of a first shallow trench isolation (STI) region and a pattern of a through substrate via (TSV) region within the first STI region; a pattern of a second STI region surrounding the first STI region, the second STI region includes a first and second layout region, the second layout region being separated from the first STI region by the first layout region, first active regions of a group of dummy devices being defined within the first layout region, and second active regions of a group of active devices being defined within the second layout region; and patterns of first gates of the group of dummy devices in the first layout region, each of the first active regions having substantially identical dimension in a first direction.