TSV Dummy Pattern Layout for Low-Capacitance Semiconductor Packaging
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Solution Overview
Problem
In semiconductor apparatuses, the use of TSVs for rewiring leads to increased parasitic capacitance when wafers are shared in manufacturing processes, resulting in reduced operation speeds and high-frequency characteristics, particularly in WLCSP and ceramic packages.
Innovation Solution
A semiconductor apparatus is designed with an opening for a pad on the front surface and a dummy pattern around a dummy non-forming region that penetrates to the wiring layer from the rear surface, reducing parasitic capacitance by optimizing the layout and shape of the dummy pattern and TSV, including a higher density of dummy wiring and islands, and varying positions and shapes to minimize capacitance and enhance mechanical strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a TSV is used to rewire the rear surface side and a solder ball is formed, then downsizing is achieved as compared with wire bonding, but parasitic capacitance between the rear surface of a substrate and a wiring layer becomes large
Solution Approach 1:
The patent extracts the harmful wiring layer from the vicinity of the TSV by creating a dummy non-forming region that removes the wiring layer in the area surrounding the TSV opening. This extraction eliminates the source of parasitic capacitance while preserving the TSV's downsizing benefit.
Solution Approach 2:
The patent applies local quality by creating a dummy pattern with specific electrical characteristics around the TSV. This dummy pattern has different properties than the normal wiring layer - it is designed to reduce parasitic capacitance locally around the TSV while maintaining overall wiring functionality elsewhere in the substrate.
2Speed
If parasitic capacitance is reduced by optimizing dummy pattern layout, then operation speeds and high-frequency characteristics are improved, but device complexity increases
Solution Approach 1:
The patent segments the substrate into different functional regions: a dummy non-forming region around the TSV where wiring is removed to reduce parasitic capacitance, and normal wiring regions elsewhere. This segmentation allows targeted optimization of operation speed in critical areas without unnecessarily complicating the entire device structure.
Solution Approach 2:
The patent applies partial action by removing wiring layer only in the specific area surrounding the TSV opening, rather than throughout the entire substrate. This dummy non-forming region is localized and targeted, reducing parasitic capacitance where it matters most while avoiding excessive complexity in non-critical areas.
Data Source
AI summary
To improve characteristics in a semiconductor apparatus manufactured from a wafer shared in a plurality of manufacturing processes. A semiconductor apparatus includes an opening for a pad, a wiring layer, and a dummy pattern. In the semiconductor apparatus, the opening for a pad is formed on a front surface of a substrate. In addition, in the semiconductor apparatus, a predetermined electrode pad is provided in the opening for a pad. In the semiconductor apparatus, a front surface-side wiring layer is formed in the substrate. In the semiconductor apparatus, a dummy pattern is formed around a dummy non-forming region penetrating up to the front surface-side wiring layer from a rear surface relative to the front surface.