TSV Electrode and Surface Conductive Layer Formation

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Solution Overview

Problem

Current semiconductor package technologies, including Through Silicon Via (TSV) techniques, face challenges in reducing manufacturing costs while maintaining high capacitance density and efficient interconnections between chips.

Innovation Solution

A method of forming a chip with a Through Silicon Via (TSV) electrode and a surface conductive layer simultaneously, using a substrate thinning process, dry etching, and electroplating to create a monolithic TSV electrode and surface conductive layer, eliminating the need for additional planarization and reducing manufacturing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If TSV electrode and surface conductive layer are formed separately, then manufacturing precision is improved, but device complexity and manufacturing cost increase

Engineering Contradiction:

ImproveTSV electrode formation precisionVSAvoidmanufacturing process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges the formation of the TSV electrode and the surface conductive layer into a single electroplating step. The conductive layer is deposited simultaneously in both the penetration via (forming TSV electrode) and the opening on the surface (forming surface conductive layer), eliminating the need for separate formation processes and reducing manufacturing complexity

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The electroplating process serves multiple functions simultaneously: it forms the TSV electrode inside the penetration via, creates the surface conductive layer in the opening, and ensures monolithic integration between them. This multi-functionality reduces the number of manufacturing steps required

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Manufacturing precision

If additional planarization process is performed, then surface conductive layer quality is improved, but manufacturing cost and time increase

Engineering Contradiction:

Improvesurface conductive layer qualityVSAvoidmanufacturing cycle time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent extracts and eliminates the additional planarization process from the manufacturing sequence. By designing the electroplating process to naturally form a planar surface conductive layer that is monolithic with the TSV electrode, the need for separate planarization steps is removed, reducing both time and cost

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The electroplating process is designed to preliminarily form the surface conductive layer with adequate planarity during the same step that creates the TSV electrode. This preliminary formation with built-in planarity eliminates the need for subsequent planarization operations

Inventive Principle:

Principle #10Preliminary action

3Ease of manufacture

If TSV electrode and surface conductive layer are formed simultaneously, then manufacturing cost is reduced, but manufacturing precision may deteriorate

Engineering Contradiction:

Improvemanufacturing costVSAvoidconductive layer formation precision

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies local quality by using a patterned material layer (photoresist) to define different regions during electroplating. The patterned layer controls where the conductive material is deposited, ensuring precise formation of the surface conductive layer in the opening while allowing TSV electrode formation in the penetration via, maintaining precision despite simultaneous formation

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach saves manufacturing costs by forming the TSV electrode and surface conductive layer in a single step, ensuring efficient interconnections and high capacitance density without additional interfaces, thus enhancing package efficiency.

Implementation Method 1

A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening

Methodology Applied

Scientific EffectElectroplating: Electroplating

Data Source

PatentUS9437491B2Method of forming chip with through silicon via electrode

Publication Date: 2016.09.06 UNITED MICROELECTRONICS CORP

AI summary

The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening.