TSV Electroplating Seed Layer via Pad for Cost Reduction
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Solution Overview
Problem
Traditional methods for creating through-silicon vias (TSVs) in semiconductor technology require expensive vacuum equipment for electrode electroplating, increasing device costs and limiting the efficiency of forming conductive connections between both sides of semiconductor components.
Innovation Solution
A method and structure for forming a package with via-holes in semiconductor devices, where a conductive via structure is formed without exceeding the opening on one side, using a first pad as a seed layer for electroplating, allowing for vertical integration of semiconductor devices and reducing the need for vacuum equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional vacuum techniques (plasma vapor deposition) are used to form seeding layers for TSV electroplating, then conductive connections can be achieved, but device costs increase due to expensive equipment requirements
Solution Approach 1:
The patent extracts and eliminates the vacuum technique step from the traditional TSV formation process. Instead of using plasma vapor deposition in a vacuum environment to form the seeding layer, the invention directly forms the conductive filling material (copper) in the via-hole through electroplating without requiring a vacuum environment, thereby removing the need for expensive vacuum equipment while maintaining conductive connection reliability
Solution Approach 2:
The patent replaces expensive vacuum equipment with simpler, less costly electroplating equipment. The seeding layer formation is integrated into the electroplating process itself, using disposable or easily replaceable electrode structures rather than requiring investment in and maintenance of expensive vacuum deposition systems
2Adaptability or versatility
If through-silicon vias are formed to connect external contacts on both sides, then electrical connections between separate wafers or chips are enabled, but the manufacturing process becomes more complex and costly
Solution Approach 1:
The patent removes the complex vacuum-based seeding layer formation step from the TSV manufacturing process. By directly electroplating copper into the via-holes without requiring plasma vapor deposition, the manufacturing process is simplified while still achieving the necessary electrical connection capability between external contacts on both sides of the semiconductor substrate
Solution Approach 2:
The patent combines the seeding layer formation and conductive filling steps into a single electroplating process. The electroplating process itself serves to both create the conductive path and form the necessary seed structure, eliminating the need for separate vacuum deposition and filling operations, thereby reducing manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach lowers production costs and enhances the electrical performance of semiconductor packages by enabling efficient conductive connections between both sides of semiconductor devices without the need for expensive vacuum techniques.
Implementation Method 1
an electrode electroplating method is used for the conductive filling materials to be disposed in the hole of the through silicon via (TSV)
Data Source
AI summary
A package structure including: a first semiconductor device including a first semiconductor substrate and a first electronic device, the first semiconductor device having a first side and a second side, wherein at least part of the first electronic device being adjacent to the first side, and the first semiconductor device has a via-hole formed through the first semiconductor device, wherein the via-hole has a first opening adjacent to the first side; an interconnection structure disposed in the first semiconductor device, wherein the interconnection structure includes: a via structure disposed in the via-hole without exceeding the first opening; a first pad disposed on the first side of the first semiconductor device and covering the via-hole; and a second semiconductor device vertically integrated with the first semiconductor device.