Semiconductor Device TSV Electroplating Seed Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing integration density in semiconductor devices leads to higher RC delay and power consumption due to increased interconnection wiring, making it challenging to manufacture reliable three-dimensional integrated circuits with smaller solder balls, which are costly and difficult to test effectively.
Innovation Solution
A semiconductor device and manufacturing method that utilize a single step of through-silicon via electroplating to form a redistribution layer, through-silicon vias, and micro bumps, with a titanium copper composite plating seed layer and anti-oxidation layer to reduce manufacturing costs and improve connectivity between vertically stacked semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single step of through-silicon via electroplating is used to form redistribution layer, TSVs, and micro bumps, then manufacturing cost is reduced and process is simplified, but manufacturing precision and reliability of smaller solder balls become more challenging
Solution Approach 1:
The patent combines the formation of redistribution layer, through-silicon vias, and micro bumps into a single electroplating step. The plating seed layer is formed on the substrate with cavities, and electroplating is performed to simultaneously create all three structures, merging multiple manufacturing steps into one operation.
Solution Approach 2:
The patent applies different materials and properties to different regions: the plating seed layer uses titanium copper composite for controlled plating, the anti-oxidation layer protects specific surfaces, and the buffer layer provides mechanical support. Each region has optimized properties for its specific function while being formed in the same process step.
2Quantity of substance
If smaller solder balls are used to increase integration density, then component density increases, but testing reliability becomes more difficult and manufacturing cost increases
Solution Approach 1:
The patent changes the material composition parameters of the solder balls by using titanium copper composite plating seed layer instead of traditional solder materials. This allows for smaller, more uniform spherical structures with controlled oxidation resistance, improving both density and reliability simultaneously.
Solution Approach 2:
The patent employs composite material structures: titanium copper composite for the plating seed layer provides both adhesion and controlled plating properties, while the anti-oxidation layer protects the micro bumps. This composite approach enables smaller, more reliable connecting elements.
3Length of moving object
If electroplate manufacturing of TSVs is used to connect vertically stacked chips, then connection distance is reduced, but manufacturing cost occupies a large portion
Solution Approach 1:
The patent merges the TSV formation with redistribution layer and micro bump creation into a single electroplating step. By forming all three structures simultaneously from a common plating seed layer, the manufacturing cost is reduced while maintaining the short connection distances required for 3DIC.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method simplifies the manufacturing process, reduces the cost of electroplating, and achieves smaller, more reliable conductive bumps with reduced gaps, enhancing the miniaturization of electronic devices and reducing the overall volume of three-dimensional integrated circuits.
Implementation Method 1
a single step of through-silicon via electroplating to simultaneously form a redistribution layer, through-silicon vias, and micro bumps
Data Source
AI summary
A semiconductor device includes a substrate, a redistribution layer, a plurality of through-silicon vias (TSVs), and a plating seed layer. The substrate has a first surface and a second surface opposite to each other, and a plurality of cavities. The redistribution layer is disposed on the first surface, and the TSVs are respectively disposed in the cavities. The plating seed layer is disposed between the inner wall of each of the cavities and the corresponding TSVs. The anti-oxidation layer is disposed between the plating seed layer and the corresponding TSVs. The buffer layer covers the first surface and exposes the redistribution layers. Furthermore, a manufacturing method and a stacking structure of the semiconductor device are also provided.