TSV-Enabled SOI Structure Without Wafer Bonding

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Solution Overview

Problem

The high cost of semiconductor-on-insulator (SOI) substrates due to the expensive SOI bonding process hinders the widespread adoption of their performance benefits in integrated circuits (ICs).

Innovation Solution

A low-cost SOI structure is formed by depositing a metal layer over an insulating layer, eliminating the need for the expensive bonding process, and incorporating through-substrate vias (TSVs) for improved electrical connectivity and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the traditional SOI bonding process is used to form semiconductor-on-insulator substrates, then the substrate achieves reduced parasitic capacitance, reduced leakage current, and improved semiconductor device performance, but the fabrication cost becomes excessively high

Engineering Contradiction:
Improvesemiconductor device performanceVSAvoidfabrication cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent replaces the expensive traditional SOI bonding process with a cost-effective alternative using disposable-like sacrificial layers (oxide layer and metal layer) that are deposited, patterned, and removed to create the desired SOI structure. This approach sacrifices the reusability and precision of bonding equipment in exchange for significantly reduced fabrication costs while maintaining the performance benefits of SOI substrates

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent changes the fundamental manufacturing parameters from thermal bonding processes to deposition and etching processes. By using atomic layer deposition (ALD) to create sacrificial oxide and metal layers, then selectively removing them to form the SOI structure, the method transforms the manufacturing approach from high-cost bonding to lower-cost deposition-based processes, achieving both cost reduction and performance maintenance

Inventive Principle:
Principle #35Parameter changes

2Reliability

If through-substrate vias (TSVs) are formed in the metal substrate layer, then electrical connectivity and device performance are improved, but the device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improveelectrical connectivityVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs preliminary actions by forming the TSV openings and isolation structures in the metal substrate layer before completing the semiconductor device fabrication. The isolation structures are deposited and patterned early in the process to define TSV locations, and the openings are created while the sacrificial layers are still in place, simplifying subsequent via formation and reducing overall manufacturing complexity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses the sacrificial oxide and metal layers as intermediary structures that facilitate TSV formation. These intermediary layers are deposited, patterned, and removed to create the TSV openings and isolation structures, serving as temporary mediators that simplify the overall TSV formation process and reduce the complexity of direct via drilling through the metal substrate

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The low-cost SOI structure achieves comparable performance to traditional SOI substrates while reducing fabrication costs, enhancing switching speed and reducing leakage current through biased metal layers.

Implementation Method 1

A low-cost SOI structure is formed by depositing a metal layer over an insulating layer

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Data Source

PatentUS12414380B2Method for forming an integrated chip (IC) including forming a through substrate via (TSV) in an isolation structure formed in a first opening that formed in a metal substrate layer
Publication Date: 2025.09.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12414380B2 patent drawing
  • US12414380B2 patent drawing
  • US12414380B2 patent drawing

AI summary

Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a substrate. The substrate includes a metal layer, a device layer disposed over the metal layer, and an insulating layer disposed vertically between the metal layer and the device layer. A semiconductor device is disposed on the device layer. An interlayer dielectric (ILD) layer is disposed over the semiconductor device and the substrate.