TSV Encapsulation Structure for Moisture-Isolated Interconnects
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Solution Overview
Problem
Moisture penetration into the front side interconnect wiring during through-silicon-via formation reduces back-end-of-line semiconductor yields and affects the reliability of the interconnect wiring.
Innovation Solution
A semiconductor structure with a TSV encapsulation and dielectric liner is formed around the top portion of the through-silicon-via hole, using known BEOL semiconductor processes, to prevent moisture ingress during TSV formation. The TSV encapsulation is composed of a refractory metal or metal nitride, surrounded by a dielectric liner, which is electrically isolated from the TSV and front side interconnect wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSV formation processes are performed without encapsulation, then manufacturing simplicity is maintained, but moisture penetration into front side interconnect wiring occurs reducing yield and reliability
Solution Approach 1:
The TSV encapsulation structure is formed in advance before the TSV etching process. The encapsulation includes a refractory metal layer deposited on the front surface of the semiconductor substrate, extending beyond the future TSV opening boundaries. This preliminary encapsulation prevents moisture and chemicals from penetrating into the front side interconnect wiring during subsequent TSV formation processes.
Solution Approach 2:
The refractory metal encapsulation acts as an intermediary barrier between the external environment (moisture and chemicals) and the front side interconnect wiring. This intermediate layer protects the sensitive interconnect wiring from direct exposure to harmful substances during TSV etching and subsequent processing steps.
2Productivity
If TSV encapsulation with refractory metal is deposited, then moisture penetration is prevented improving yield, but additional manufacturing steps are required
Solution Approach 1:
The refractory metal encapsulation is deposited using physical vapor deposition (PVD) or chemical vapor deposition (CVD) processes before TSV etching. The encapsulation layer is patterned to extend beyond the future TSV opening boundaries, creating a protective rim that prevents moisture ingress during subsequent processing steps.
Solution Approach 2:
The refractory metal material properties (high melting point, chemical stability) are utilized to create an effective barrier against moisture and chemical penetration. The deposition parameters (thickness, coverage area) are controlled to ensure adequate protection while managing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability and yield of the front side interconnect wiring by preventing moisture and chemical penetration during TSV formation, thereby improving the integrity and performance of the semiconductor chip.
Implementation Method 1
A TSV encapsulation contacts the sidewall of the dielectric liner, where the TSV encapsulation resides on the top surface of the semiconductor substrate
Implementation Method 2
A dielectric liner contacts a sidewall of the top portion of the TSV, where the dielectric liner resides on at least a top surface of a plurality of front side interconnect wiring layers
Implementation Method 3
The interlayer dielectric material separates the moisture oxidation collar from the plurality of front side interconnect wiring layers surrounding the moisture oxidation collar
Data Source
AI summary
A semiconductor structure that with a via last through-silicon-via hole that has a dielectric liner surrounds a sidewall of the top portion of the through-silicon-via hole that is above and contacting the top surface of the semiconductor substrate. A through-silicon-via encapsulation is directly on and surrounds the dielectric liner around the top portion of the through-silicon-via hole. The through-silicon-via encapsulant can be composed of a refractory metal that is electrically isolated from the completed through-silicon-via by at least the dielectric liner.