TSV Encapsulation Layering for Thermal-Cycle-Reliable Semiconductor Packages

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Solution Overview

Problem

Semiconductor packages face challenges in achieving high performance, high capacity, and miniaturization while maintaining reliability, particularly due to issues with through-silicon vias (TSV) in existing manufacturing methods.

Innovation Solution

A method involving the formation of semiconductor packages with encapsulation layers comprising a mixture of organic resin and inorganic filler, which includes forming insulating and electrode pads, bonding semiconductor chips, etching to expose TSVs, and creating redistribution structures for improved electrical connectivity and thermal cycle reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional encapsulation methods are used for TSV structures, then manufacturing is simpler, but cracking and void formation occur during thermal cycling reducing reliability

Engineering Contradiction:

Improvethermal cycle reliabilityVSAvoidencapsulation process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The encapsulation process is divided into multiple steps: forming a protective layer over TSVs before encapsulation, selective removal of the protective layer to expose TSVs, and controlled encapsulation. This segmentation allows each step to be optimized independently, preventing cracking while managing process complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A protective layer is formed over the TSVs before the encapsulation process begins. This preliminary action protects the TSVs from damage during subsequent encapsulation steps, preventing void formation and cracking that would otherwise occur with conventional direct encapsulation methods.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If TSVs are exposed to form redistribution structures, then electrical connectivity is improved, but the risk of cracking and void formation increases

Engineering Contradiction:

Improveelectrical connectivityVSAvoidcracking and void formation

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The protective layer is applied in advance to counteract the harmful effects of exposure during redistribution structure formation. This preliminary protective measure prevents cracking and void formation while still allowing the TSVs to be exposed for electrical connectivity when needed.

Inventive Principle:

Principle #9Preliminary anti-action

Solution Approach 2:

The protective layer is selectively removed only from specific regions where TSV exposure is needed for redistribution structures, while maintaining protection in other areas. This local quality approach ensures electrical connectivity where required while preventing cracking and voids in protected regions.

Inventive Principle:

Principle #3Local quality

3Volume of moving object

If miniaturization is pursued to fit smaller electronic devices, then device size is reduced, but manufacturing precision requirements increase

Engineering Contradiction:

Improvesemiconductor package sizeVSAvoidTSV alignment and encapsulation precision

Core Design Contradiction:

Volume of moving objectVSManufacturing precision

Solution Approach 1:

The protective layer is formed before dicing and packaging operations, establishing precise alignment references early in the process. This preliminary action maintains manufacturing precision even as device size is reduced for miniaturization applications.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Multiple functional layers are nested within the semiconductor structure, with the protective layer integrated into the encapsulation flow. This nesting approach consolidates multiple precision requirements into a unified process, managing manufacturing precision demands during miniaturization.

Inventive Principle:

Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The encapsulation layer with a high-modulus material enhances thermal cycle reliability by preventing cracking and void formation, thus improving the overall reliability and performance of semiconductor packages.

Implementation Method 1

wet-etching a surface of the semiconductor chip to expose the through-silicon via

Methodology Applied

Scientific EffectWet etching:

Implementation Method 2

covering the exposed through-silicon via with a material, including an organic resin and an inorganic filler, to form an encapsulation layer

Methodology Applied

Scientific EffectEncapsulation:

Implementation Method 3

grinding an upper surface of the second encapsulation layer to expose the through-silicon via

Methodology Applied

Scientific EffectGrinding: Abrasion

Implementation Method 4

bonding the first insulating layer and the first electrode pad of the semiconductor chip to the second insulating layer and the second electrode pad of the semiconductor wafer

Methodology Applied

Scientific EffectBonding:

Data Source

PatentUS12519079B2Method of manufacturing semiconductor package

Publication Date: 2026.01.06 SAMSUNG ELECTRONICS CO LTD

AI summary

A method of manufacturing a semiconductor package includes: hybrid-bonding a semiconductor chip, including a through-silicon via, to an upper surface of a semiconductor wafer, wet-etching a surface of the semiconductor chip to expose the through-silicon via, covering the exposed through-silicon via with a material, including an organic resin and an inorganic filler, to form an encapsulation layer, removing an upper surface of the encapsulation layer to expose the through-silicon via, and forming a redistribution structure electrically connected to the through-silicon via.