Buried Etch Stop Layer for Uniform TSV Depth Control
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Solution Overview
Problem
Existing methods for producing through-silicon vias (TSVs) in semiconductor devices struggle to achieve uniform depth across a wafer, leading to inconsistent electrical properties and difficulties in contacting TSVs of varying depths.
Innovation Solution
A method involving a silicon wafer with raised portions as placeholders, an etch stop layer, and temporary/ permanent wafer bonding to define and limit the etching process, ensuring uniform TSV depth through a buried three-dimensional etch stop layer, allowing for different TSV geometries with consistent depth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used to produce TSVs, then the etching can be completed, but the TSV depth becomes non-uniform across the wafer
Solution Approach 1:
An etch stop layer is deposited on the front surface of the silicon wafer before the TSV etching process. This preliminary action creates a reference structure that defines the maximum etch depth, ensuring that all TSVs across the wafer reach a uniform depth when they encounter this stop layer during backside etching.
Solution Approach 2:
The solution introduces a new dimensional reference (the etch stop layer position) that transforms the depth control problem from a vertical measurement challenge into a lateral reference plane problem. By creating a physical barrier at a specific depth position, the system converts complex depth uniformity control into a simpler stop-condition etching process.
2Adaptability or versatility
If TSVs with different geometries are produced, then design flexibility is improved, but depth consistency becomes difficult to maintain
Solution Approach 1:
The etch stop layer is selectively positioned at different lateral locations corresponding to different TSV sites, allowing each TSV to have its own customized geometry (cylindrical, conical, stepped, etc.) while all of them terminate at the same depth defined by the etch stop layer. This enables local geometric variation without compromising global depth consistency.
Solution Approach 2:
The wafer surface is divided into multiple regions, each with its own etch stop layer structure tailored to the specific TSV geometry requirements of that region. This segmentation allows different TSV types to coexist on the same wafer while maintaining uniform depth through the common principle of etching to the stop layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the production of TSVs with uniform depth and varied geometries on a single wafer, optimizing electrical properties and facilitating efficient contacting of components, thereby enhancing the versatility and performance of semiconductor devices.
Implementation Method 1
depositing an etch stop layer on the first surface of the silicon wafer; etching a plurality of trenches into the silicon wafer using a masked etching process, proceeding from the second surface of the silicon wafer; Integrating the buried etch stop layer in the silicon substrate, i.e. in the combination of silicon wafer and first carrier wafer, during the etching process allows the length and depth of the individual TSVs to be defined
Implementation Method 2
providing a silicon wafer having a plurality of raised portions of equal height on a first surface of the silicon wafer as a placeholder for through-silicon vias; each trench being formed at the respective location of one raised portion of the plurality of raised portions
Implementation Method 3
depositing side wall insulation layers made of insulating material on side walls of the trenches
Implementation Method 4
forming through-silicon vias by filling the trenches with electrically conductive material
Implementation Method 5
permanently bonding a first carrier wafer to the surface of the etch stop layer; temporarily bonding a second carrier wafer onto a surface of the conductor path stack
Data Source
AI summary
Method for producing a semiconductor device by providing a silicon wafer having a plurality of equal height raised portions on a first surface thereof; depositing an etch stop layer on the first surface; planarizing a surface of the etch stop layer; permanently bonding a first carrier wafer on the etch stop layer surface; producing components on or in a second wafer surface in a FEOL process; etching a plurality of trenches into the wafer, each trench formed at the respective location of one of the raised portions; depositing side wall insulation layers on side walls of the trenches; forming through-silicon vias by filling the trenches with electrically conductive material; producing a conductor path stack in a BEOL process for contacting the active components on the second surface; temporarily bonding a second carrier wafer onto a surface of the conductor path stack; removing the first carrier wafer and exposing the vias.