3D Semiconductor Package Using TSV-Free Copper Direct Bonding
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Solution Overview
Problem
Current three-dimensional integrated circuits (3DICs) face challenges in meeting semiconductor industrial requirements due to structural defects and fabrication complexity associated with through-silicon-via (TSV) structures, which hinder efficient integration and signal transmission.
Innovation Solution
A semiconductor package is fabricated using copper-to-copper direct bonding in a chip-to-wafer manner, replacing the TSV structure with a conductive structure disposed at a higher location than the chip, simplifying the fabrication process and improving structural reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon-via (TSV) structures are used to achieve three-dimensional integrated circuits, then vertical interconnection and signal transmission are enabled, but fabrication complexity and structural defects increase
Solution Approach 1:
The patent extracts and removes the TSV structure from the semiconductor package, replacing it with a planar interconnection structure. This eliminates the complex via formation process while maintaining electrical interconnection functionality between stacked chips, thereby reducing fabrication complexity without compromising structural reliability
Solution Approach 2:
Instead of creating vertical connections through silicon substrates (TSV approach), the patent inverts the interconnection strategy by using planar copper interconnection structures on the chip surfaces. This inversion simplifies the fabrication process while achieving the same goal of vertical signal transmission through stacked chip architecture
2Productivity
If TSV structures are implemented for chip stacking, then three-dimensional integration is achieved, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent segments the interconnection function from the substrate structure by using separate planar copper interconnection layers instead of integrated TSV structures. This segmentation allows for simpler, more cost-effective manufacturing processes while maintaining high integration efficiency through the stacked chip architecture
3Device complexity
If copper-to-copper direct bonding is used instead of TSV, then fabrication complexity is reduced, but new bonding process requirements are introduced
Solution Approach 1:
The patent changes the bonding parameters and process conditions by implementing copper-to-copper direct bonding at controlled temperatures and pressures. This parameter optimization enables simplified fabrication while accommodating the specific requirements of copper bonding, achieving both reduced complexity and process adaptability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication complexity and cost of TSV structures, enhances structural reliability, and facilitates the arrangement of input/output terminals, making the semiconductor package suitable for thin and short packaging applications.
Implementation Method 1
the present disclosure is directed to provide a semiconductor package, a semiconductor bonding structure, and a method of fabricating the same, in which the semiconductor package is fabricated by copper-to-copper direct bonding in a chip-to-wafer bonding manner
Data Source
AI summary
The present disclosure relates to a semiconductor package, a semiconductor bonding structure and a method of fabricating the same. The semiconductor package includes a first chip, a second chip and a conductive structure, wherein the conductive structure is disposed at a side of the second chip and over a second upper surface of the first interconnection structure to electrically connect to the first interconnection structure. The semiconductor bonding structure includes a first substrate, a plurality of first interconnection structures, a plurality of chips and a plurality of conductive structures, wherein the conductive structures are respectively disposed at a side of each of the chips and over a second upper surface of each first interconnection structure, to electrically connect to each first interconnection.