TSV Gap-Fill and ILD Protection via Etch Stop Layer
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Solution Overview
Problem
The formation of through-silicon-vias (TSVs) in 3D integrated circuits poses challenges, particularly due to excessive loss of interlayer dielectric (ILD) layers during chemical mechanical polish (CMP) processes, which can damage gate structures and worsen with advanced technology nodes having reduced ILD thickness and tighter process windows.
Innovation Solution
A method involving the formation of a TSV structure with a wider opening near the top to facilitate better gap-fill of conductive materials, reducing the risk of over-polishing and ILD layer damage, includes depositing a dielectric layer that lines the TSV opening, patterning to create a wider opening for the metal layer, and filling with conductive materials, followed by CMP to remove excess material, ensuring the ILD layer's integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If CMP process is used to remove excess TSV material, then TSV structure is formed, but ILD layer is excessively removed damaging gate structures
Solution Approach 1:
An etch stop layer is deposited over the ILD layer before forming the TSV opening. This preliminary action creates a protective barrier that prevents excessive removal of the ILD layer during subsequent CMP processes, thereby protecting gate structures while enabling TSV formation.
Solution Approach 2:
The etch stop layer acts as an intermediary between the ILD layer and the TSV structure. During CMP processing, this intermediate layer controls the removal rate, allowing excess TSV conductive material to be removed while stopping before damaging the underlying ILD layer and gate structures.
2Productivity
If ILD thickness is reduced for advanced technology nodes, then device density is improved, but process window is tightened increasing damage risk
Solution Approach 1:
The etch stop layer is deposited in advance before TSV formation, creating a controlled interface that enables precise CMP stopping. This preliminary structure allows for reduced ILD thickness in advanced nodes while maintaining adequate process margins to prevent gate structure damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the risk of damaging gate structures and enhances gap-fill efficiency, maintaining ILD layer integrity and enabling more reliable TSV formation, even in advanced technology nodes.
Implementation Method 1
The substrate is then subjected to a chemical mechanical polish (CMP) process, such that the excess oxide liner and the TSV metallic material that are over the ILD layer are removed
Data Source
AI summary
A structure includes a substrate, and an interconnect structure over the substrate. The structure further includes a through-substrate-via (TSV) extending through the interconnect structure and into the substrate, the TSV comprising a conductive material layer. The structure further includes a dielectric layer having a first portion over the interconnect structure and a second portion within the TSV, wherein the first portion and the second portion comprise a same material. The conductive material layer includes a first section separated from substrate by the second portion of the dielectric layer. The conductive material layer further includes a second section over a top surface of the second portion of the dielectric layer. The conductive material layer further includes a third section over the second section, wherein the third section has a width greater than a width of the second section.