Low Stress Thin Film Gap Layer for TSV Devices
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Solution Overview
Problem
Through silicon via (TSV) structures experience tensile stresses due to thermal expansion mismatches, leading to performance drift and micro-crack formation in silicon interposers during temperature excursions, as existing air gaps fail to adequately reduce stress.
Innovation Solution
A low stress, thin film gap layer is introduced between TSVs and transistors, filled with a suitable material to control stresses and maintain a spatial distance, reducing adverse effects of temperature excursion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If air gaps are used between TSV and transistors, then some stress reduction is achieved, but the stress is not adequately reduced leading to performance drift and micro-crack formation
Solution Approach 1:
The patent changes the material parameter of the gap fill from air (vacuum) to a solid dielectric material with specific mechanical properties. This parameter change transforms the gap from providing minimal stress relief to actively managing and reducing stress through the mechanical properties of the solid fill material, thereby preventing performance drift and micro-crack formation while maintaining device reliability.
Solution Approach 2:
The solid dielectric fill material acts as an intermediary between the TSV and the transistors. Instead of leaving a direct air gap that provides insufficient stress management, the solid material mediates the stress interaction, absorbing and distributing thermal expansion stresses to protect the transistors from stress-induced damage.
2Device complexity
If no gap layer is present, then device complexity is reduced, but tensile stresses from thermal expansion mismatch cause performance drift and micro-cracks
Solution Approach 1:
The gap layer is formed preliminarily before the transistors are positioned and connected to the TSVs. This preliminary structural preparation ensures that the stress-buffering mechanism is already in place before thermal cycling occurs during operation, preventing tensile stresses from causing performance drift or micro-cracks without requiring complex real-time adjustment mechanisms.
3Reliability
If a solid dielectric fill material is used in the gap layer, then stress control is improved, but manufacturing process complexity increases
Solution Approach 1:
The solid dielectric fill material serves multiple functions simultaneously: it provides stress control by buffering thermal expansion mismatches, acts as an electrical insulator between the conductive TSV and surrounding structures, and maintains the structural integrity of the gap region. This multi-functionality reduces the need for additional separate components or processes, thereby limiting the increase in manufacturing complexity while significantly improving stress control capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The low stress thin film gap layer effectively mitigates stress-induced performance drift and micro-crack formation by maintaining a buffer zone between TSVs and transistors, enhancing the reliability of TSV devices.
Implementation Method 1
The gap layer is typically filled with a low stress, thin film fill material that controls stresses and crack formations on the devices
Implementation Method 2
When the operational temperature is higher than the stress-free temperature, expansion of metal within a via will induce tensile stresses (e.g., in circumferential directions) in silicon interposers due to a mismatch of coefficients of thermal expansion
Data Source
AI summary
Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress, thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.