TSV Grain Distribution to Reduce Interface Voiding
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Solution Overview
Problem
As the minimum feature sizes in semiconductor devices are reduced, challenges such as RC delay and void aggregation at the interfaces of conductive through-substrate vias (TSVs) arise, affecting the integration density and reliability of 3DICs.
Innovation Solution
The implementation of a metallization process to achieve a Large-Small-Large (LSL) grain distribution in conductive TSVs, utilizing a specific sequence of forming adhesive and barrier layers, removing the inner adhesive layer, and performing an anneal process to form alloys with controlled grain growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional metallization process is used to form conductive TSVs, then the TSVs can be formed to connect integrated circuits, but void aggregation occurs at the TSV interfaces reducing reliability
Solution Approach 1:
The patent applies local quality by creating different grain sizes at different locations within the TSV. The metallization process forms large grains at the interface regions (top and bottom of the TSV) and smaller grains in the middle portion. This non-uniform grain distribution locally optimizes the interface regions to prevent void aggregation, while the middle portion maintains different characteristics. The selective grain size control at specific locations directly addresses the void aggregation problem at TSV interfaces.
Solution Approach 2:
The patent changes the grain size parameter of the conductive material along the length of the TSV. By controlling the metallization process (including annealing conditions), the invention creates a gradient in grain size - large grains at the interfaces and smaller grains in the middle. This parameter change in grain structure fundamentally alters the stress distribution and prevents void formation at the critical interface regions, thereby improving reliability.
2Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated, but RC delay increases affecting performance
Solution Approach 1:
The patent changes the physical parameters of the conductive material by controlling grain size distribution. The large grains at the TSV interfaces reduce electrical resistance by providing fewer grain boundaries for electron scattering. This parameter change in the conductive material's microstructure directly addresses the RC delay issue, allowing smaller feature sizes to be used without proportionally increasing resistance and maintaining performance while achieving higher integration density.
3Productivity
If standard metallization process is used, then the process is simple and fast, but stress distribution is uneven causing voiding issues
Solution Approach 1:
The patent applies local quality by creating large grains specifically at the stress-prone interface regions of the TSV. The metallization process is controlled to form different grain structures at different locations - large grains where stress concentrates (at the interfaces) and smaller grains in the middle. This localized grain structure optimization addresses the stress distribution issue without requiring complete process redesign, maintaining productivity while improving stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach optimizes stress and voiding distribution in TSVs, achieving 100% yield during fabrication by reducing void aggregation at the TSV interfaces and improving thermal stability of the conductive material.
Implementation Method 1
performing an anneal process to form alloys with controlled grain growth
Implementation Method 2
anneal process to form alloys with controlled grain growth
Data Source
AI summary
Conductive vias, semiconductor devices with conductive vias, and methods for fabricating semiconductor devices are provided. A conductive via includes a first end and a second end; a first portion adjacent to the first end; a second portion adjacent to the second; and a middle portion located between the first portion and the second portion, wherein the conductive via is comprised of metal grains, the metal grains in the first portion have a first grain size; the metal grains in the second portion have a second grain size; the metal grains in the middle portion have a third grain size; the first grain size is greater than the third grain size; and the second grain size is greater than the third grain size.