Concentric TSV Guard Rings for Lower Parasitic Capacitance

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Solution Overview

Problem

The increasing complexity and feature size reduction in integrated circuits exacerbate signal delay due to the RC time constant, which is exacerbated by the capacitance contribution from metal interconnect structures, particularly in semiconductor back-end-of-line processing, where low-k dielectric materials are susceptible to damage and degradation during processing.

Innovation Solution

A guard ring structure is introduced around through-silicon via (TSV) structures, comprising concentric guard rings that extend through a subset of inter-metal dielectric (IMD) layers to reduce parasitic capacitance and protect against contaminant diffusion, thereby enhancing signal transport speed and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If low-k dielectric material is used to form IMD layers to reduce capacitance, then signal transport speed is improved, but the dielectric material becomes susceptible to damage and degradation during processing

Engineering Contradiction:
Improvesignal transport speedVSAvoidsusceptibility to damage during processing
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

A guard ring structure is introduced as an intermediary element between the low-k dielectric material and processing contaminants. The guard ring acts as a protective barrier that prevents contaminant diffusion into the low-k material during etching, deposition, and wet processes, thereby protecting the dielectric from damage while maintaining its low capacitance properties

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The guard ring structure is formed in advance before the low-k dielectric material undergoes processing. This pre-formed protective structure cushions and protects the low-k material from potential damage during subsequent manufacturing steps, preventing degradation before it can occur

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Speed

If metal interconnect structures are fabricated with IMD layers to achieve desired signal transport, then interconnect functionality is achieved, but capacitance contribution increases RC time constant delay

Engineering Contradiction:
Improvesignal transport speedVSAvoidRC time constant delay
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The guard ring structure extracts or removes the harmful parasitic capacitance effect from the interconnect system. By introducing a grounded guard ring, the parasitic capacitance between adjacent signal lines is eliminated, thereby reducing the RC time constant and improving signal transport speed

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The guard ring structure effectively reduces parasitic capacitance and protects against contaminant diffusion, improving signal transport speed and reliability in semiconductor circuits by isolating the TSV structures and reducing the electrical impact of the guard rings on the TSVs.

Implementation Method 1

reduce parasitic capacitance between the TSV structures and surrounding conductive elements

Methodology Applied
Scientific EffectParasitic capacitance: Parasitic Capacitance

Implementation Method 2

protect against contaminant diffusion

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS12027475B2Semiconductor die including guard ring structure and three-dimensional device structure including the same
Publication Date: 2024.07.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12027475B2 patent drawing
  • US12027475B2 patent drawing
  • US12027475B2 patent drawing

AI summary

A die includes: a semiconductor substrate; an interconnect structure disposed on the semiconductor substrate and including: inter-metal dielectric (IMD) layers; metal features embedded in the IMD layers; and a guard ring structure including concentric first and second guard rings that extend through at least a subset of the IMD layers; and a through silicon via (TSV) structure extending through the semiconductor substrate and the subset of IMD layers to electrically contact one of the metal features. The first guard ring surrounds the TSV structure; and the second guard ring surrounds the first guard ring and is configured to reduce a parasitic capacitance between the guard ring structure and the TSV structure.