Multi-Chip Semiconductor Module With TSV Half-Bridge Layout
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Solution Overview
Problem
In power conversion applications, the close placement of transistors within a single package is hindered by the need for minimal spacing between individual chips, leading to increased stray inductivities and limitations in package shrinkage due to practical issues with chip placement and spacing.
Innovation Solution
A multi-chip module is developed that enables closer chip spacing and direct electrical connection between source and drain using through silicon vias (TSVs), allowing for the formation of a half bridge configuration within a standard plastic package or for chip embedding, with the module fabricated using a method involving trench formation, polymer layer application, and metallization to reduce lateral area occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If packages are mounted on circuit board with conductive redistribution structure, then electrical coupling between semiconductor devices is achieved, but lateral area occupied is undesirably large
Solution Approach 1:
The patent merges multiple semiconductor devices into a single integrated semiconductor chip, combining what were previously separate packages into one unified component. This integration eliminates the need for external conductive redistribution structures on circuit boards, thereby reducing the lateral area occupied while maintaining all necessary electrical connections within the chip itself.
Solution Approach 2:
The patent transitions from a two-dimensional layout where packages are mounted on a circuit board to a three-dimensional integrated structure where devices are stacked or arranged vertically within a single chip. This dimensional change allows electrical connections to be made through vertical interconnects rather than lateral traces, significantly reducing the footprint area.
2Area of stationary object
If minimal spacing is maintained between individual chips, then lateral area is reduced, but stray inductivities increase
Solution Approach 1:
By merging multiple devices into a single integrated chip with internal interconnects, the patent eliminates the external package-to-package connections that generate stray inductivities. The internal connections within the integrated chip have much lower inductance due to shorter trace lengths and optimized current paths, thus reducing harmful stray inductivities while maintaining compact area.
Solution Approach 2:
The patent extracts the problematic external connection structures (packages and board-mounted redistributors) that create high stray inductivities, replacing them with integrated on-chip interconnects. This removal of external connection layers eliminates the primary source of stray inductance while preserving the electrical functionality.
3Area of stationary object
If chip spacing is reduced, then package size is minimized, but practical issues with chip placement and spacing arise
Solution Approach 1:
The patent combines multiple previously separate chips into a single integrated semiconductor chip, eliminating the need for separate chip placement operations. This integration resolves practical placement issues by treating multiple devices as one unit, allowing standard packaging and mounting processes to be used without concern for minimal spacing between individual chips.
Solution Approach 2:
The patent segments the integrated chip into distinct functional regions or device areas internally, allowing each virtual 'chip' to be designed and fabricated independently on the same substrate before final integration. This segmentation enables optimized layout for minimal spacing while maintaining manufacturability through standard semiconductor fabrication processes.
Data Source
Figure 1
Figure 2
Figure 3A~3B
AI summary
In an embodiment, a module comprises a first electronic device in a first device region and a second electronic device in a second device region. The first electronic device is operably coupled to the second electronic device to form a circuit. Side faces of the first electronic device and of the second electronic device are embedded in, and in direct contact with, the first epoxy layer.