Localized TSV Heating for IC Defect Detection
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Solution Overview
Problem
The challenge is to detect defects in integrated circuits due to through silicon vias (TSVs) without subjecting the IC chip to high temperatures, as traditional methods require heating the entire chip wafer, which can be time-consuming and may damage the plastic substrate used in thinned IC chips that cannot withstand temperatures above 50°C.
Innovation Solution
A circuit integrated into the IC chip at the wafer level for localized heating and temperature control, using a parallel heating structure with heating elements in a metal layer, coupled to a test control system that can measure current transfer and vary temperature from 25°C to 300°C, allowing precise detection of defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional high-temperature testing methods are used to detect defects, then defect detection capability is improved, but the plastic substrate may be damaged due to excessive temperature
Solution Approach 1:
The heating function is segmented from the entire wafer level heating to localized heating elements integrated at specific device locations. This allows temperature control to be applied locally only where needed for defect detection, rather than heating the entire plastic substrate which would cause damage.
Solution Approach 2:
Temperature control is applied locally at device-level rather than uniformly across the entire wafer. Heating elements are positioned adjacent to specific devices and can independently control temperature at those locations, enabling defect detection without subjecting the plastic substrate to damaging high temperatures.
2Measurement precision
If the entire chip wafer is heated to high temperatures for defect detection, then defect visibility is improved, but testing time increases significantly
Solution Approach 1:
The testing process is segmented to allow parallel temperature control and measurement operations. Multiple heating elements can operate simultaneously at different locations, and the multiplexer enables rapid switching between measurement points, reducing total testing time while maintaining defect detection capability.
Solution Approach 2:
The system dynamically controls temperature at multiple locations independently and switches measurement points rapidly using a multiplexer. This dynamic operation allows efficient data collection from multiple devices without requiring sequential heating of the entire wafer, significantly reducing testing time.
3Device complexity
If wafer level integration of heating and measurement circuits is implemented, then device complexity is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The heating elements, measurement circuits, and control logic are merged into a single integrated test structure at the wafer level. This consolidation reduces the number of separate components and interconnections needed, simplifying the overall device architecture while the standardized integration process manages manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables precise detection of defects and reliability issues in IC chips with TSV architecture by controlling temperature locally, improving defect detection capabilities and addressing the limitations of traditional high-temperature testing methods.
Implementation Method 1
a parallel heating structure adjacent to the plurality of devices electrically coupled to the test control system, wherein the heating elements are formed in a metal layer of a plurality of metal layers over the first silicon layer
Data Source
AI summary
A device and method to control the heating of an IC chip in a wafer form for measuring various parameters associated therewith are provided. Embodiments include a device having a silicon layer with an upper surface, and on a plastic carrier; a plurality of devices in the silicon layer and electrically coupled through the upper surface to a test control system; a through silicon via (TSV) extending into the silicon layer; and a parallel heating structure adjacent to the plurality of devices electrically coupled to the test control system.