Through Silicon Via Formation via Hydrophobic Surface Treatment
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Solution Overview
Problem
In semiconductor device manufacturing, the formation of through silicon via holes often results in voids due to uneven surface morphology and impurity layer patterns, which can affect the quality and reliability of the device.
Innovation Solution
A method involving sequential dry-etching of silicon substrates using fluorine and carbon-based gases to form sub-via holes and passivation layers, followed by treatment with hydrofluoric acid solutions to create hydrophobic surfaces, allowing for uniform deposition of insulating layers and subsequent filling with conductive materials, thereby reducing void formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching and filling methods are used to form through silicon via holes, then the manufacturing process is simple, but voids are formed due to uneven surface morphology and impurity layer patterns
Solution Approach 1:
The patent applies preliminary action by performing surface treatment (hydrophobic modification) and selective removal of impurity layer patterns before filling the via hole with conductive material. This preparatory treatment of the via hole inner surface ensures uniform insulating layer deposition and prevents void formation, directly addressing the quality issue while maintaining process feasibility through sequential straightforward steps
2Ease of manufacture
If the insulating layer is deposited on impurity layer patterns, then the deposition process is straightforward, but voids are formed due to uneven surface morphology
Solution Approach 1:
The patent applies the extraction principle by selectively removing impurity layer patterns from the via hole inner surface using targeted etching processes. By extracting only the problematic impurity layers while preserving the underlying structure, the surface becomes suitable for uniform insulating layer deposition, ensuring via hole quality without complicating the overall manufacturing process
Solution Approach 2:
The patent performs preliminary surface treatment including hydrophobic modification before insulating layer deposition. This preliminary action creates a uniform surface energy distribution that enables consistent deposition coverage, preventing void formation while maintaining ease of manufacture through a straightforward sequential process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures the formation of void-free through silicon via holes, enhancing the quality and reliability of semiconductor devices by improving surface morphology and reducing the likelihood of voids during conductive material filling.
Implementation Method 1
performing dry-etching on the semiconductor substrate to form the via hole, wherein the semiconductor substrate is a silicon substrate. The dry-etching of the silicon substrate may comprise forming a sub-via hole exposing side walls of the silicon substrate by etching the silicon substrate using a first gas comprising fluorine
Implementation Method 2
forming a passivation layer pattern on the side walls of the silicon substrate exposed by the sub-via hole using a second gas comprising carbon
Implementation Method 3
treating an upper surface and the side walls of the insulating interlayer pattern exposed by the via hole, the treated upper surface and side walls of the insulating interlayer pattern being hydrophobic
Data Source
AI summary
The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern.