TSV Inductor Interposer Layout for High-Q Semiconductor Packages
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Solution Overview
Problem
Conventional semiconductor packages face challenges in achieving high quality factor (Q factor), small area consumption, limited parasitic coupling, and ease of layout and manufacture, particularly due to the need for additional metal layers that increase on-die area and fabrication costs.
Innovation Solution
A semiconductor package design featuring a first die with through-silicon vias (TSVs) penetrating through a silicon substrate, an interposer layer with an inductor directly coupled to the TSVs, and a second die stacked on the first die, where the inductor is placed in the interposer layer to efficiently utilize silicon area and connect to front-side circuits through TSVs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional metal layers are used to improve Q factor, then quality factor is improved, but on-die area increases and fabrication costs increase
Solution Approach 1:
The inductor is moved from the on-die plane to the interposer layer beneath the first die, utilizing the vertical dimension and substrate space. This dimensional transition allows the inductor to be formed in a separate layer without occupying valuable on-die area, while still providing electrical connection to the TSVs through the interposer structure.
Solution Approach 2:
An interposer layer is introduced as an intermediary structure between the first die and the substrate. This interposer contains the inductor and provides electrical interconnection between the TSVs of the first die and the inductor circuit, enabling the inductor to be coupled to TSVs without requiring additional metal layers on the die itself.
2Reliability
If additional metal layers are used to improve Q factor, then quality factor is improved, but fabrication costs increase
Solution Approach 1:
The interposer layer serves as a mediator that consolidates the inductor formation process in a dedicated layer beneath the die, rather than requiring multiple additional metal layers to be deposited and patterned on the die itself. This approach simplifies the overall fabrication process and reduces manufacturing complexity and costs.
Solution Approach 2:
By forming the inductor in the interposer layer rather than adding metal layers to the die, the invention utilizes the vertical stacking architecture to achieve inductor integration without increasing the lateral fabrication process complexity, thereby reducing fabrication costs.
3Reliability
If additional metal layers are used to improve Q factor, then quality factor is improved, but fabrication throughput decreases
Solution Approach 1:
The interposer layer with the inductor is prepared in advance before the first die is mounted. This preliminary preparation of the inductor circuit in the interposer allows subsequent die attachment and wire bonding to proceed without interruption, maintaining high fabrication throughput while achieving improved Q factor.
Data Source
AI summary
A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.