3D Inductor and Transformer Using TSV Interconnects
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high-density integration of inductors and transformers due to physical limits in two-dimensional (2D) designs, which result in increased resistance and unwanted noise from magnetic flux coupling with other components on the chip.
Innovation Solution
A three-dimensional (3D) inductor and transformer design using an interposer with through-substrate vias (TSVs) and conductive bumps to form coils, allowing for larger conductive materials and reduced magnetic flux penetration, thereby increasing the quality factor and reducing parasitic coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 2D integration is used to integrate inductors and transformers on the chip, then device integration is achieved, but the chip area occupied is large and resistance increases
Solution Approach 1:
The patent transitions from 2D planar integration to 3D vertical integration by stacking multiple metallization layers (first through fourth metallization layers) at different heights and connecting them through TSVs. This dimensional change allows inductors and transformers to be formed in three-dimensional space, significantly increasing integration density while reducing the chip area occupied by these components.
2Productivity
If feature sizes are reduced to increase integration density, then more components fit on the chip, but metal line resistance increases
Solution Approach 1:
By stacking multiple metallization layers vertically and connecting them through TSVs to form three-dimensional coil structures, the patent increases the effective conductor cross-sectional area without increasing the planar footprint. This 3D configuration maintains lower resistance even as feature sizes are reduced, preserving the quality factor while achieving higher integration density.
Solution Approach 2:
The patent employs composite conductive structures formed by combining multiple metallization layers with different materials and configurations. The stacked metallization layers with TSV interconnects create a composite conductor that effectively reduces resistance compared to single-layer planar structures, maintaining reliability as integration density increases.
3Productivity
If inductors and transformers are placed on the chip, then integration is achieved, but magnetic flux couples with other devices creating noise
Solution Approach 1:
The patent forms inductors and transformers using stacked metallization layers connected by TSVs, creating three-dimensional coil structures. This 3D configuration directs magnetic flux primarily in the vertical direction, parallel to the chip surface, rather than allowing flux to penetrate through the chip and couple with other devices. The vertical orientation of the magnetic field reduces parasitic coupling with planar devices on the chip.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D design enables higher quality factor inductors and transformers, reduces parasitic coupling, and allows for more compact and cost-effective integration by utilizing thicker conductive materials and directing magnetic flux parallel to the chip surface.
Implementation Method 1
At least one TSV electrically couples one of the first conductive pattern and the second conductive pattern to one of the third conductive pattern and the fourth conductive pattern to form a first coil
Implementation Method 2
conductive bumps bonding the semiconductor die to the interposer
Data Source
AI summary
In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.