TSV Stair-Shaped Inner Wall for CTE-Induced Crack Resistance
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Solution Overview
Problem
In silicon photonic devices, cracks often occur due to CTE mismatch between materials at the junction of through silicon vias (TSVs), insulation layers, and semiconductor dies during temperature and humidity tests, exacerbated by the straight and continuous inner walls of through holes acting as lever arms that concentrate stress.
Innovation Solution
The semiconductor package design features a semiconductor substrate with a through hole having a stair-shaped inner wall and stress raisers, where the length of the lever arm is less than the substrate thickness, and includes a second stress raiser to distribute stress, reducing the concentration at the junction and preventing cracks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a through hole with straight and continuous inner wall is used, then electrical connection is achieved, but stress concentration occurs at the junction due to lever arm effect
Solution Approach 1:
The inner wall of the through hole is segmented into multiple sections with different orientations rather than being straight and continuous. This segmentation creates multiple stress paths and eliminates the lever arm effect that causes stress concentration at the junction, thereby improving crack resistance without compromising electrical connection.
Solution Approach 2:
The inner wall structure is made asymmetric by introducing sections with different orientations. This asymmetric design disrupts the uniform stress distribution that occurs with straight walls, preventing stress concentration at the junction while maintaining the through-hole's electrical connection function.
2Adaptability or versatility
If materials with different CTE are used for TSV and insulation layer, then functional requirements are met, but cracks occur during temperature and humidity test
Solution Approach 1:
The inner wall is divided into multiple segments with different orientations, which distributes the thermal stress caused by CTE mismatch across multiple interfaces rather than concentrating it at a single junction. This segmentation allows the use of materials with different CTE values while preventing crack formation during temperature and humidity testing.
Solution Approach 2:
Different sections of the inner wall are given different orientations to locally accommodate thermal expansion differences. This local variation in geometry allows the structure to handle CTE mismatch between materials while maintaining overall reliability and preventing cracks during environmental testing.
3Strength
If lever arm length is increased, then structural support is improved, but stress concentration at junction is exacerbated
Solution Approach 1:
The inner wall is segmented into multiple sections, which breaks the continuous lever arm structure. This segmentation maintains structural support through the distributed geometry while eliminating the stress concentration mechanism that occurs in continuous lever arms, thereby reducing junction stress.
Solution Approach 2:
The inner wall incorporates curved or angled sections instead of straight lines, creating a non-linear path. This curvature disrupts the lever arm effect that causes stress concentration while still providing the necessary structural support for the through-hole configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces stress at the junction, as demonstrated by simulation results, thereby eliminating or avoiding cracks and enhancing the reliability of the semiconductor package.
Implementation Method 1
Due to CTE mismatch between materials of different layers of the TSV, cracks may occur during temperature and humidity test
Data Source
AI summary
A semiconductor package includes a first die. The first die includes a semiconductor substrate. The semiconductor substrate has a first surface, a second surface opposite to the first surface, and a through hole between the first surface and the second surface and having an inner wall. The inner wall has a first lever arm. A length of the first lever arm is less than a thickness of the semiconductor substrate.