TSV Surrounding Insulation for High-Voltage Breakdown Control
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Solution Overview
Problem
As semiconductor devices are scaled down, parasitic capacitance among gate stacks becomes a challenge due to reduced spacing, affecting device performance, and high voltages can lead to dielectric breakdown between through-silicon via (TSV) structures and the substrate.
Innovation Solution
The implementation of second insulating features surrounding the TSV structure, which are electrically coupled to the substrate, maintains a consistent voltage potential and reduces electric fields, thereby preventing dielectric breakdown and metal diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If through-silicon via (TSV) structures are used for vertical interconnect, then device integration density is improved, but dielectric breakdown between TSV and substrate occurs under high voltage
Solution Approach 1:
An insulating structure is introduced as an intermediary element between the TSV and the substrate. This insulating structure surrounds the TSV and is electrically coupled to the substrate, creating a protective barrier that prevents direct electrical interaction between the TSV and substrate, thereby preventing dielectric breakdown while maintaining the TSV's vertical interconnect function
Solution Approach 2:
The insulating structure is electrically coupled to the substrate to maintain a consistent voltage potential between the TSV and substrate interface. By establishing equipotential conditions, the electric field strength is reduced, preventing dielectric breakdown of the surrounding insulation layers under high voltage conditions
2Productivity
If gate stack spacing is reduced to increase device density, then device integration is improved, but parasitic capacitance among gate stacks increases
Solution Approach 1:
Mandrel structures are introduced as intermediary elements between adjacent gate stacks. These mandrels are positioned between the gate stacks and extend along the channel region, serving as electrical barriers that reduce parasitic capacitance coupling between neighboring gate stacks while allowing the gate stacks to remain in close proximity for high density integration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design mitigates dielectric breakdown and metal diffusion, enabling high-voltage applications by maintaining consistent voltage potential and reducing electric fields around the TSV structure.
Implementation Method 1
maintains a consistent voltage potential and reduces electric fields, thereby preventing dielectric breakdown
Data Source
AI summary
The present disclosure provides a semiconductor device. The semiconductor device includes: a substrate having a device area and a peripheral area surrounding the device area; a via, disposed at the peripheral area and extending at least partially through the substrate; an insulating structure, disposed at the peripheral area, extending at least partially through the substrate and surrounding the via; and a doped region, disposed at the peripheral area, over or in the substrate and adjacent to the via.