TSV Insulation via Thermal Oxidation and SACVD

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Solution Overview

Problem

Traditional via etching processes in through-silicon via (TSV) fabrication result in scallop-like shapes with micro-concaves, leading to uneven sidewall insulation, voids in conductor-filled vias, and increased parasitic capacitance, which complicates the achievement of high breakdown voltage and uniform insulation necessary for reliable TSV connections.

Innovation Solution

The implementation of a dual-layer sidewall insulation structure using different deposition methods for the first and second insulation layers, with a thermal oxidation process for the first layer and SACVD or PECVD for the second layer, to achieve smooth interfaces with peak-to-valley roughness less than 5 nm, optimizing electrical characteristics and reducing stress and cracking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional via etching process is used, then via formation is achieved, but sidewall shows scallop-like shapes with micro-concaves causing uneven insulation and voids

Engineering Contradiction:
Improvesidewall uniformityVSAvoidinsulation quality
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

A mandrel structure is formed at the bottom of the via opening before insulation deposition. This preliminary structure serves as a foundation that enables subsequent insulation layers to achieve uniform thickness coverage on the scalloped sidewalls, preventing void formation and ensuring reliable insulation quality.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The mandrel acts as an intermediary structure between the scalloped via sidewalls and the insulation layers. It provides a stable base that allows insulation material to deposit uniformly, mediating the interface between the rough etched surface and the smooth insulation requirement.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If single-layer insulation structure is used, then process simplicity is maintained, but uniform insulation thickness and electrical performance cannot be achieved

Engineering Contradiction:
Improveinsulation thickness uniformityVSAvoidinsulation structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The insulation structure is divided into multiple layers: a first insulation layer deposited directly on the scalloped sidewalls, and a second insulation layer deposited over the first layer. This segmentation allows each layer to serve specific functions - the first layer fills irregularities while the second layer provides uniform thickness, achieving both coverage and precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the via structure receive different insulation treatments. The mandrel region receives specialized insulation deposition to ensure uniform coverage on scalloped surfaces, while other regions receive standard insulation. This local differentiation optimizes insulation quality where needed without unnecessarily complicating the entire structure.

Inventive Principle:
Principle #3Local quality

3Reliability

If insulation is deposited on scalloped sidewalls, then via isolation is achieved, but stress and cracking increase

Engineering Contradiction:
Improvevia isolationVSAvoidinsulation layer integrity
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The mandrel is formed as a preliminary stress-distributing structure before insulation deposition. It provides a mechanically stable foundation that reduces stress concentration on the scalloped sidewalls during insulation layer formation, preventing cracking and maintaining insulation layer integrity.

Inventive Principle:
Principle #10Preliminary action

4Productivity

If conventional etching is used, then via formation speed is maintained, but parasitic capacitance increases due to uneven sidewalls

Engineering Contradiction:
Improvevia formation speedVSAvoidparasitic capacitance
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The mandrel structure is extracted or removed after insulation deposition is complete. This removal eliminates the source of parasitic capacitance associated with the scalloped sidewalls, while the insulation layers that were deposited over the mandrel remain to provide low-capacitance isolation between vias.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures uniform insulation thickness, reduces silicon and layer cracks, enhances process reliability, and mitigates the trade-offs between insulation film quality and step-coverage, resulting in improved electrical performance and reliability of TSV connections.

Implementation Method 1

a thermal oxidation process for the first layer

Methodology Applied
Scientific EffectThermal oxidation: Oxidation

Implementation Method 2

SACVD or PECVD for the second layer

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Data Source

PatentUS9087878B2Device with through-silicon via (TSV) and method of forming the same
Publication Date: 2015.07.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9087878B2 patent drawing
  • US9087878B2 patent drawing
  • US9087878B2 patent drawing

AI summary

A method includes forming an opening extending from a top surface of a silicon substrate into the silicon substrate to a predetermined depth. The method further includes forming an insulation structure on the silicon substrate along the sidewalls and the bottom of the opening and forming a conductive layer on the insulation structure to fill the opening. A first interface between the insulation structure and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm, and a second interface between the insulation structure and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm.