Through-Via Insulation Thickness Control for TSV Reliability

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Solution Overview

Problem

Existing semiconductor device fabrication methods face challenges in ensuring the reliability and yield of through-silicon vias (TSVs) due to contamination and particle issues caused by exposed TSVs during the via-insulating layer etching process.

Innovation Solution

A method involving the formation of a via-insulating layer with a thicker bottom surface thickness and a thinner sidewall thickness, using flowable chemical vapor deposition (FCVD) layers, and subsequent recessing of the substrate to expose the through-via, while maintaining electrical insulation and preventing substrate exposure, is employed to improve the fabrication process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the via-insulating layer is etched to recess the substrate, then the through-via can be exposed for electrical connection, but the exposed through-via becomes a contamination or particle source causing process errors

Engineering Contradiction:
Improveexposure precision of through-viaVSAvoidcontamination and particle contamination
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The via-insulating layer is formed in advance with a thicker bottom surface thickness before substrate recessing. This preliminary thicker layer ensures that even after etching and recessing, the through-via remains covered and does not become exposed to cause contamination or particle issues, while still allowing precise electrical connection when needed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The via-insulating layer is designed with non-uniform thickness: a first (thicker) thickness on the bottom surface of the via-hole and a second (thinner) thickness on the inner sidewall. This local quality differentiation allows the bottom surface to provide sufficient coverage preventing exposure and contamination, while the thinner sidewall portion maintains electrical insulation without excessive material.

Inventive Principle:
Principle #3Local quality

2Reliability

If the via-insulating layer thickness is increased to prevent through-via exposure, then contamination is prevented, but the electrical insulation effectiveness may be compromised

Engineering Contradiction:
Improvecontamination preventionVSAvoidelectrical insulation effectiveness
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The via-insulating layer employs different thicknesses at different locations: a thicker first thickness on the bottom surface to prevent through-via exposure and contamination, and a thinner second thickness on the inner sidewall to maintain appropriate electrical insulation. This local quality variation optimizes both contamination prevention and electrical insulation effectiveness.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The via-insulating layer is effectively segmented into two functional regions: the bottom surface portion with greater thickness for mechanical coverage and contamination prevention, and the sidewall portion with lesser thickness for electrical insulation. This segmentation allows each region to perform its specific function optimally.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the reliability and yield of semiconductor devices by preventing contamination and particle exposure, ensuring effective electrical insulation and minimizing process errors, thereby improving the electric characteristics of the devices.

Implementation Method 1

converting the flowable layer into a first flowable chemical vapor deposition layer having the first thickness on the bottom surface of the via-hole

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Data Source

PatentUS9362172B2Semiconductor devices having through-vias and methods for fabricating the same
Publication Date: 2016.06.07 SAMSUNG ELECTRONICS CO LTD
  • US9362172B2 patent drawing
  • US9362172B2 patent drawing
  • US9362172B2 patent drawing

AI summary

The inventive concept provides semiconductor devices having through-vias and methods for fabricating the same. The method may include forming a via-hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a via-insulating layer having a first thickness on a bottom surface of the via-hole and a second thickness smaller than the first thickness on an inner sidewall of the via-hole, forming a through-via in the via-hole which the via-insulating layer is formed in, and recessing a bottom surface of the substrate to expose the through-via. Forming the via-insulating layer may include forming a flowable layer on the substrate, and converting the flowable layer into a first flowable chemical vapor deposition layer having the first thickness on the bottom surface of the via-hole.