Through Silicon Via Contact for Integrated Circuit Integration Density
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Solution Overview
Problem
Existing methods for power semiconductor components require complex and serial connections at the housing level, limiting integration density and increasing overhead, as they necessitate contacting both sides of the integrated circuit through mold compounds.
Innovation Solution
The implementation of through silicon vias (TSV) allows for internal contact connections within the wafer, enabling direct electrical connections between the front and back sides of the chip, eliminating the need for external housing-level contacts and reducing the complexity of mold compound-based interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard housing connections with wires or clips are used for contacting power semiconductor components, then electrical connections can be established, but integration density is limited and integration overhead increases due to serial and complex connection processes
Solution Approach 1:
The patent merges the contact area and connection function into a single integrated structure. The contact area on the semiconductor chip serves dual purposes: as the electrical contact point and as the connection terminal, eliminating the need for separate wires or clips. This integration reduces the number of components and simplifies the connection process while maintaining reliable electrical contact.
Solution Approach 2:
The patent extracts the connection function from the housing level and integrates it directly into the semiconductor chip structure. By forming contact areas directly on the chip that extend through the semiconductor layer, the connection function is embedded within the device itself, removing the need for external wiring and reducing overall device complexity.
2Reliability
If both front side and back side of the power integrated circuit are contacted at the housing level through mold compound, then electrical connections are achieved, but integration density is limited and manufacturing processes become more complex
Solution Approach 1:
The patent transitions from a planar two-sided contact approach to a vertical through-contact architecture. Contact areas are formed that extend through the semiconductor layer from the front side to the back side, enabling electrical connections to be established in the vertical dimension rather than requiring separate front and back side contacts at the housing level. This dimensional change simplifies the manufacturing process by reducing the number of separate contact operations required.
3Productivity
If through silicon vias are used for internal contact connections, then integration density is enhanced and serial processes are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary formation of contact areas during the semiconductor fabrication process itself, before the chip is packaged. The contact areas are created as part of the standard semiconductor manufacturing sequence, integrating the connection structure formation into the existing fabrication flow. This preliminary action approach leverages the precision capabilities of established semiconductor manufacturing equipment while maintaining high integration density.
Data Source
AI summary
An integrated circuit is provided, the integrated circuit including: a chip having a first chip side and a second chip side opposite to the first chip side, the chip having at least one contact area on the second chip side; encapsulation material at least partially covering the chip; and at least one contact via comprising electrical conductive material contacting the at least one contact area and extending through the encapsulation material and through the chip between the first chip side and the second chip side.