TSV Integration Before Contacts for 3D Chip Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor chip bonding methods limit the integration of through substrate vias (TSVs) to after contacts and transistors are applied, leading to surface space loss, unreliable regions in 3D stacks, and increased resistivity, which slows down chip speed and restricts wiring flexibility.
Innovation Solution
A novel method of integrating TSVs by forming them before contacts, involving steps like etching trenches, depositing dielectric materials, polishing, building CMOS devices, applying contamination barriers, and metalizing the TSVs, allowing for pre-contact TSV integration and flexible wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSVs are created after contacts and transistors are applied to chips, then the chip structure can be built, but surface space is lost and unreliable regions are created in 3D stacks
Solution Approach 1:
The patent applies preliminary action by forming TSVs in the substrate before applying contacts and transistors. This sequence allows TSVs to be established as reliable vertical interconnects prior to device fabrication, eliminating the creation of unreliable regions in 3D stacks and preserving maximum surface space for active devices.
2Speed
If TSVs are inserted last, then the chip structure is complete, but contacts must be made of tungsten which increases resistivity and slows down chip speed
Solution Approach 1:
By performing TSV formation before contact fabrication, the patent enables the use of copper or other low-resistivity materials for contacts instead of being forced to use tungsten. This preliminary sequencing allows optimization of contact material selection for minimum resistivity, thereby maximizing chip speed.
Solution Approach 2:
The invention changes the material parameter of contacts from tungsten (high resistivity) to copper or alternative materials (low resistivity) by altering the process sequence. This parameter change directly reduces contact resistivity and improves signal transmission speed.
3Adaptability or versatility
If TSVs are created last, then the chip is fully fabricated, but wiring must be done around TSVs which restricts design flexibility
Solution Approach 1:
The patent applies preliminary action by establishing TSVs before device and interconnect fabrication. This sequencing allows wiring to be performed over and around TSVs without restriction, providing complete design flexibility for interconnect routing while maintaining efficient fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces process complexity, enables the use of copper contacts, allows for back-end wiring freedom, and uses low-k dielectrics, resulting in reliable contacts and improved chip performance with flexible design options.
Implementation Method 1
depositing one or more dielectric materials into the one or more trenches
Implementation Method 2
polishing the wafer to remove any excess dielectric material from the one or more trenches
Implementation Method 3
plating the one or more wafer holes with a conductor
Implementation Method 4
annealing the wafer to promote any of the conductor from the through substrate vias to expand out of the one or more wafer holes
Data Source
AI summary
An apparatus and method are provided for integrating TSVs into devices prior to device contacts processing. The apparatus includes a semiconducting layer; one or more CMOS devices mounted on a top surface of the semiconducting layer; one or more TSVs integrated into the semiconducting layer of the device wafer; at least one metal layer applied over the TSVs; and one or more bond pads mounted onto a top layer of the at least one metal layer, wherein the at least one metal layer is arranged to enable placement of the one or more bond pads at a specified location for bonding to a second device wafer. The method includes obtaining a wafer of semiconducting material, performing front end of line processing on the wafer; providing one or more TSVs in the wafer; performing middle of line processing on the wafer; and performing back end of line processing on the wafer.