TSV Integrity Testing Before Chip Stacking
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Solution Overview
Problem
The existing semiconductor chip packaging processes face challenges in testing the integrity and yield of through silicon vias (TSVs) before chip stacking, leading to wasted resources and increased costs due to the lack of effective pre-stacking reliability testing methods.
Innovation Solution
A method involving the formation of blind holes in a wafer, deposition of an insulating layer, and creation of conductive posts, followed by a mechanical integrity test using external forces to assess the conductive posts' binding strength, allowing for the identification of defective TSVs before further processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional package testing methods are used after chip stacking, then the testing can be performed, but the cost and time are wasted when TSV defects are detected too late
Solution Approach 1:
The patent performs TSV integrity testing at an intermediate stage during the fabrication process, before chip stacking is completed. This preliminary testing allows defects to be detected early, preventing waste of subsequent fabrication time and resources that would be spent on assembling defective chips into stacks.
2Reliability
If conventional package testing methods are used after chip stacking, then the testing can be performed, but the cost increases due to wasted resources on defective TSVs
Solution Approach 1:
The patent performs TSV integrity testing at an intermediate stage during the fabrication process, before chip stacking is completed. This preliminary testing allows defects to be detected early, preventing waste of subsequent fabrication resources and costs that would be incurred if defective chips were assembled into stacks only to be found defective later.
3Reliability
If TSV integrity testing is performed before chip stacking, then the yield can be improved, but no effective testing method existed previously
Solution Approach 1:
The patent replaces conventional mechanical testing methods (such as shear tests on solder balls or wire bonding hook tests) with an electrical testing approach. By applying electrical signals to the TSV structures and measuring their response, the integrity of TSVs can be assessed without requiring complex mechanical testing apparatus or destructive mechanical forces.
Data Source
AI summary
A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test.