TSV Interconnect Structures for Semiconductor Core Die
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Solution Overview
Problem
Current semiconductor manufacturing methods for vertical electrical interconnections, such as through hole vias (THVs) and through silicon vias (TSVs), are time-consuming, costly, and prone to defects due to the need for temporary carriers and complex electroplating processes, which hinder the production of smaller, more efficient semiconductor devices.
Innovation Solution
The development of semiconductor devices with topside and bottom-side interconnect structures formed around a core die using through silicon vias (TSVs), which eliminate the need for temporary carriers and simplify the interconnection process by forming conductive layers and insulating layers to connect the TSVs directly, enabling efficient vertical electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through hole vias (THVs) or through silicon vias (TSVs) are used for vertical electrical interconnections, then electrical connectivity is achieved, but manufacturing time increases and production efficiency decreases
Solution Approach 1:
The patent removes the temporary carrier from the final product structure. The carrier is used only during the via formation process to provide structural support, then it is discarded after serving its purpose. This extraction of the unnecessary component reduces manufacturing complexity and improves productivity while maintaining via formation capability.
Solution Approach 2:
The patent performs preliminary structural preparation by bonding the semiconductor die to the package substrate before via formation. This preliminary action provides the necessary structural support to eliminate the need for a temporary carrier during subsequent via formation steps, thereby reducing manufacturing time and improving production efficiency.
2Reliability
If electroplating processes are used to fill vias with conductive material, then electrical conductivity is improved, but manufacturing costs increase
Solution Approach 1:
The patent employs a disposable temporary carrier that is used only during the via formation and filling processes. This carrier enables the use of cost-effective via formation methods without requiring expensive permanent structural support elements. After serving its purpose, the carrier is discarded, having enabled cost reduction in the overall manufacturing process.
3Stability of the object's composition
If temporary carriers are used to support package substrate during via formation, then structural stability is maintained, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the temporary carrier from the final product structure. By using the carrier only temporarily during via formation and then removing it, the patent reduces the number of components and process steps required, thereby reducing device complexity while maintaining structural stability during the critical via formation phase.
Solution Approach 2:
The patent performs preliminary bonding of the semiconductor die to the package substrate to establish structural stability before via formation. This preliminary action eliminates the need for a temporary carrier, thereby reducing process complexity while maintaining the necessary structural support throughout the via formation process.
4Reliability
If via filling processes are performed, then electrical interconnection is completed, but manufacturing time increases
Solution Approach 1:
The patent performs preliminary bonding of the semiconductor die to the package substrate with contact pads exposed, creating a structurally stable configuration that eliminates the need for temporary carriers during via formation. This preliminary preparation enables faster via formation and filling processes by removing setup and removal steps for temporary support structures, thereby reducing overall manufacturing time while completing the electrical interconnection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing time and costs, enhances production efficiency, and improves the reliability of semiconductor devices by providing a more straightforward and effective method for vertical electrical interconnections, facilitating the creation of smaller, higher-performance devices.
Implementation Method 1
a first conductive via formed through the first semiconductor die... The topside and bottom-side interconnect structures are electrically connected through the core TSV die
Data Source
AI summary
A semiconductor device has a core semiconductor device with a through silicon via (TSV). The core semiconductor device includes a plurality of stacked semiconductor die and semiconductor component. An insulating layer is formed around the core semiconductor device. A conductive via is formed through the insulating layer. A first interconnect structure is formed over a first side of the core semiconductor device. The first interconnect structure is electrically connected to the TSV. A second interconnect structure is formed over a second side of the core semiconductor device. The second interconnect structure is electrically connected to the TSV. The first and second interconnect structures include a plurality of conductive layers separated by insulating layers. A semiconductor die is mounted to the first interconnect structure. The semiconductor die is electrically connected to the core semiconductor device through the first and second interconnect structures and TSV.