TSV Interconnect Elevator Chip Stacking Reducing FPGA Costs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current Field Programmable Gate Array (FPGA) semiconductor ICs face challenges due to larger size, higher fabrication costs, and increased Non-Recurring Engineering (NRE) costs when transitioning to advanced technology nodes, hindering innovation and adoption of advanced semiconductor technology.
Innovation Solution
The development of a Vertical Interconnect Elevator (VIE) chip or component using Through-Silicon-Via Interconnect Elevator (TSVIE) technology for 3D chiplet systems, enabling vertical interconnection between semiconductor IC chips without requiring Through Silicon Vias (TSVs, and allowing for the stacking of chip packages using Package-On-Package assembly methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Through-Silicon-Via (TSV) technology is used for vertical interconnection, then interconnection efficiency is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent segments the TSV structure into multiple functional layers: copper seed layer, barrier layer, conductive fill, and cap layer. Each layer performs a specific function (adhesion, diffusion prevention, electrical conduction, protection), allowing complex TSV interconnection to be achieved through systematic modular fabrication steps rather than monolithic processing
Solution Approach 2:
The patent introduces intermediary layers between the silicon substrate and upper interconnect structures. The barrier layer (e.g., tungsten nitride or titanium nitride) acts as an intermediary to prevent copper diffusion into silicon, while the cap layer serves as an intermediary protective layer during subsequent processing steps, simplifying the overall manufacturing by preventing defects
2Productivity
If advanced technology nodes (below 20 nm) are adopted, then performance is improved, but Non-Recurring Engineering (NRE) cost increases greatly
Solution Approach 1:
The patent develops a universal TSV fabrication methodology that can be applied across multiple technology nodes and device types. The same barrier layer materials (tungsten nitride, titanium nitride), conductive fill processes (electroplating, electroless plating), and cap layer structures serve multiple functions: adhesion promotion, diffusion barrier, electrical conduction, and mechanical support, making the process universally applicable and reducing NRE costs
Solution Approach 2:
The patent systematically adjusts process parameters (layer thicknesses, material compositions, deposition temperatures, plating currents) to optimize TSV performance for different technology nodes. By establishing parameter scaling relationships, the same fundamental process flow can be adapted to advanced nodes without requiring complete process re-development, thereby reducing NRE expenditures
3Reliability
If larger semiconductor chip size is used for FPGA, then fabrication yield is improved, but fabrication cost and power consumption increase
Solution Approach 1:
The patent transitions from planar chip expansion to vertical three-dimensional integration using TSV technology. Instead of increasing chip lateral dimensions to accommodate more logic elements, the design stacks multiple logic layers vertically connected by TSVs, achieving higher functionality without proportionally increasing fabrication cost or power consumption
Data Source
AI summary
A method for a through-silicon-via (TSV) connector includes: providing a semiconductor wafer with a silicon substrate, wherein the semiconductor wafer has a frontside and a backside opposite to the frontside thereof; forming multiple holes in the silicon substrate of the semiconductor wafer; forming a first insulating layer at a sidewall and bottom of each of the holes; forming a metal layer over the semiconductor wafer and in each of the holes; polishing the metal layer outside each of the holes to expose a frontside surface of the metal layer in each of the holes; forming multiple metal bumps or pads each on the frontside surface of the metal layer in at least one of the holes; grinding a backside of the silicon substrate of the semiconductor wafer to expose a backside surface of the metal layer in each of the holes, wherein the backside surface of the metal layer in each of the holes and a backside surface of the silicon substrate of the semiconductor wafer are coplanar; and cutting the semiconductor wafer to form multiple through-silicon-via (TSV) connectors.