3D Chip Package with TSV Interconnect Elevator for Flexible Stacking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3D IC chip packaging technologies face challenges in efficiently providing vertical interconnects for signal, clock, power, and ground connections between semiconductor IC chips and VIE components, particularly in multi-chip packages, where existing solutions lack flexibility and scalability in design and manufacturing processes.
Innovation Solution
The development of a Vertical Interconnect Elevator (VIE) chip or component, including Through-Silicon-Via Interconnect Elevators (TSVIE), Through-Glass-Via Interconnect Elevators (TGVIE), and Through-Polymer-Via Interconnect Elevators (TPVIE), which utilize through vias for vertical interconnections, allowing for the creation of single-chip or multi-chip packages with flexible dimensions and layouts, and enabling the stacking of chip packages using Package-On-Package assembly methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon-via interconnect elevators are used for vertical interconnection in 3D chip packages, then connectivity between chips is improved, but manufacturing complexity increases
Solution Approach 1:
The system is divided into separate functional components: VIE chips that provide through-via interconnections are distinct from the semiconductor IC chips they interconnect. This segmentation allows each component to be manufactured and optimized independently, with VIE chips serving as dedicated interconnection intermediaries that simplify the overall manufacturing process while maintaining reliable vertical connectivity.
2Adaptability or versatility
If VIE chips are used to provide vertical interconnects, then design flexibility is improved, but device complexity increases
Solution Approach 1:
VIE chips serve as universal interconnection components that can be used across different package configurations and chip types. The through-via elevator chips provide a standardized interface for vertical interconnection, enabling designers to flexibly configure 3D stacked packages without redesigning the interconnection architecture for each specific application.
Solution Approach 2:
VIE chips act as intermediary components between the semiconductor IC chips, providing a standardized mediation layer for vertical signal transmission. This intermediary approach simplifies the interconnection structure by introducing a dedicated component that handles the complexity of through-via formation and signal routing, allowing the IC chips themselves to remain relatively simple.
3Speed
If through vias are used for signal interconnection, then connectivity speed is improved, but manufacturing precision requirements increase
Solution Approach 1:
The through-via structures are formed and established in the VIE chips during their manufacturing process before the final assembly with the IC chips. This preliminary formation of interconnection pathways allows for precise via creation under controlled manufacturing conditions, and the subsequent assembly process simply needs to align with these pre-formed structures, reducing the overall precision requirements compared to forming vias during final assembly.
Data Source
AI summary
A chip package includes a first interconnection scheme; a plurality of first metal contacts under and on the first interconnection scheme and at a bottom surface of the chip package; a first semiconductor IC chip over the first interconnection scheme; a first connector over the first interconnection scheme and at a same horizontal level as the first semiconductor IC chip, wherein the first connector comprises a first substrate and a plurality of first through vias vertically extending through the first substrate of the first connector; a first polymer layer over the first interconnection scheme, wherein the first polymer layer has a top surface coplanar with a top surface of the first semiconductor IC chip, a top surface of the first substrate of the first connector and a top surface of each of the plurality of first through vias; and a second interconnection scheme on the top surface of the first polymer layer, the top surface of the first semiconductor IC chip, the top surface of the first connector and the top surface of each of the plurality of first through vias, wherein the second interconnection scheme comprises a plurality of second metal contacts at a top surface of the chip package.