Semiconductor Device With TSV Interconnects for IR Drop Reduction
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Solution Overview
Problem
Interconnecting disparate semiconductor dies to achieve desired functionalities without interference is challenging due to issues such as IR drop and structural failures in existing packaging solutions, which affect the efficiency and compactness of electronic devices.
Innovation Solution
The use of multiple redistribution layers and through silicon vias (TSVs) with underfill materials to interconnect semiconductor devices, allowing for closer placement of voltage regulators to switching loads and providing additional structural support and isolation, thereby reducing IR drop and enhancing manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If semiconductor dies are interconnected using existing packaging solutions, then functional integration is achieved, but IR drop and structural failures occur
Solution Approach 1:
The patent transitions from planar interconnection to three-dimensional vertical interconnection using through-silicon vias (TSVs). Multiple redistribution layers are stacked vertically and connected through TSVs, enabling power delivery in the vertical dimension rather than relying solely on horizontal plane connections. This dimensional change reduces current path length and resistance, eliminating IR drop while maintaining structural integrity.
Solution Approach 2:
The patent employs composite material structures including stacked redistribution layers with alternating conductive and dielectric materials, combined with underfill materials in the grooves. This composite approach provides both electrical connectivity and mechanical reinforcement, preventing structural failures while enabling functional integration of multiple semiconductor dies.
2Ease of manufacture
If voltage regulators are placed away from switching loads, then manufacturing is simpler, but IR drop increases reducing energy efficiency
Solution Approach 1:
The patent enables close placement of voltage regulators to switching loads by utilizing vertical stacking through TSVs. Power can be delivered vertically through multiple redistribution layers and TSVs, allowing regulators to be positioned adjacent to loads in the vertical dimension without increasing horizontal trace length. This maintains ease of manufacture while dramatically improving energy efficiency by reducing IR drop.
3Loss of energy
If multiple redistribution layers are used with TSVs, then IR drop is reduced, but device complexity increases
Solution Approach 1:
The patent designs redistribution layers and TSVs to serve multiple functions simultaneously. The same vertical interconnection structure provides both power delivery and signal routing, while the underfill materials in grooves provide both mechanical support and stress relief. This multi-functionality reduces energy loss through optimized power delivery without proportionally increasing device complexity.
4Strength
If underfill materials are used in grooves, then structural protection is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates underfill material placement into the groove structures during the fabrication process itself, rather than as a separate post-processing step. The grooves are formed simultaneously with the redistribution layers and TSVs, and underfill materials are applied in the same manufacturing sequence. This preliminary integration enhances structural protection while minimizing additional manufacturing complexity.
Data Source
AI summary
A method and device are provided wherein a first semiconductor device and a via are encapsulated with an encapsulant. A redistribution layer connects the first semiconductor device to a second semiconductor device. In a particular embodiment the first semiconductor device is an integrated voltage regulator and the second semiconductor device is a logic device such as a central processing unit.