3D IC Package Assembly with TSV Interconnects for Thinner Substrates
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Solution Overview
Problem
Current 3D integration technologies in IC packages do not support the use of thinner package substrates, such as bumpless build-up layers, which limits the miniaturization and performance enhancement of mobile devices in terms of processing speed and memory capacity.
Innovation Solution
The implementation of a 3D integrated circuit package assembly configuration that includes a first die embedded in a package substrate with a second die coupled through through-silicon vias (TSVs) and an adhesive layer, where an opening in the adhesive layer exposes TSV pads for direct interconnects, enabling a conductive path and allowing for thinner, coreless substrates and enhanced integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional 3D integration technologies are used, then processing speed and memory capacity can be improved, but package substrate thickness cannot be reduced
Solution Approach 1:
The patent transitions from conventional 2D package substrate integration to 3D vertical integration using through-silicon vias (TSVs). Multiple dies are stacked vertically and interconnected through TSVs that penetrate the substrate thickness, enabling high-speed processing and increased memory capacity while reducing the overall package footprint and substrate thickness requirements.
Solution Approach 2:
The patent embeds multiple functional dies within a compact package structure. A first die is embedded in the package substrate, while a second die is coupled through TSVs, creating a nested configuration where smaller functional units are integrated within a larger package assembly, maximizing space utilization and enabling thinner substrates.
2Length of stationary object
If thinner package substrates are used, then device miniaturization is improved, but mechanical strength and warpage resistance deteriorate
Solution Approach 1:
The patent employs a composite package structure combining organic package substrate material with embedded semiconductor dies and TSV interconnects. This composite construction distributes mechanical stresses across multiple materials with complementary properties, enhancing overall structural strength and warpage resistance even when the substrate thickness is reduced for miniaturization.
Solution Approach 2:
The package structure is segmented into multiple functional layers including the package substrate, embedded first die, TSV interconnects, and coupled second die. This segmentation allows each component to be optimized independently for its mechanical properties, with the TSVs providing structural reinforcement that compensates for reduced substrate thickness.
Data Source
AI summary
Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as well as corresponding fabrication methods and systems incorporating such 3D IC package assemblies. A bumpless build-up layer (BBUL) package substrate may be formed on a first die, such as a microprocessor die. Laser radiation may be used to form an opening in a die backside film to expose TSV pads on the back side of the first die. A second die, such as a memory die stack, may be coupled to the first die by die interconnects formed between corresponding TSVs of the first and second dies. Underfill material may be applied to fill some or all of any remaining gap between the first and second dies, and/or an encapsulant may be applied over the second die and/or package substrate. Other embodiments may be described and/or claimed.