TSV Interconnection Line Segmentation for Stress Relief
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional stacked semiconductor packages using metallic wires suffer from low operating speed and degraded electrical characteristics due to signal exchange through wires, and packages become larger and taller due to wire bonding, while TSV-based packages face stress-related disconnection issues between upper and lower memory chips.
Innovation Solution
The semiconductor device employs through-silicon-vias (TSVs) coupled with interconnection lines that are designed with equally divided regions to reduce stress, using internal interconnection lines and contacts to distribute and manage signal transmission effectively, thereby preventing disconnection between stacked memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If metallic wires are used for electrical coupling between stacked semiconductor chips, then the package can be fabricated with simple structure, but the operating speed is low and electrical characteristics are degraded
Solution Approach 1:
The patent replaces the mechanical wire bonding system with an electrical field-based TSV system. Instead of using physical metallic wires that require wire bonding processes and create mechanical connections, the invention uses through-silicon vias that establish direct electrical pathways through the substrate, eliminating the mechanical bonding process and improving operating speed while reducing package height.
Solution Approach 2:
The patent introduces TSVs as intermediary conductive structures that facilitate electrical coupling between stacked chips. The TSVs act as vertical interconnection mediators that replace the need for lateral wire routing, enabling direct vertical electrical pathways through the substrate and improving signal transmission characteristics.
2Area of stationary object
If metallic wires are used for electrical coupling, then the package structure can be simple, but the package size increases due to additional area for wire bonding
Solution Approach 1:
The patent transitions from lateral wire routing in the horizontal plane to vertical through-substrate connections in the vertical dimension. By routing signals vertically through TSVs rather than laterally through wire bonds on the substrate surface, the design eliminates the need for additional wire bonding area and reduces the overall package footprint.
3Speed
If TSV is used to couple stacked semiconductor chips, then operating speed is improved, but stress causes disconnection between upper and lower memory chips
Solution Approach 1:
The patent segments the interconnection line into multiple sections by introducing via holes at regular intervals along the TSV. This segmentation divides the continuous stress path into discrete segments, allowing stress to be distributed and released at each via interface rather than accumulating along the entire TSV length, thereby preventing disconnection while maintaining high-speed operation.
4Reliability
If TSV with continuous interconnection line is used, then electrical coupling is achieved, but stress on the interconnection line causes disconnection
Solution Approach 1:
The continuous interconnection line is segmented into multiple sections by introducing via holes at regular intervals. This creates a series of short-segmented conductive paths instead of one long continuous path, distributing mechanical stress across multiple via interfaces and preventing stress concentration that would lead to disconnection, while maintaining electrical coupling functionality.
Solution Approach 2:
The via holes are pre-positioned along the TSV interconnection line to act as stress relief points before stress can accumulate to critical levels. This beforehand cushioning approach proactively distributes stress along the interconnection path, preventing future disconnection issues while maintaining reliable electrical coupling.
Data Source
AI summary
A semiconductor device includes a through-silicon-via arranged to couple a plurality of stacked semiconductor chips, an interconnection line coupled to the through-silicon-via at one side and arranged to couple the through-silicon-via to the semiconductor chip, an internal interconnection line disposed at the other side of the interconnection line and intersected with the interconnection line, and at least one first contact disposed to couple the internal interconnection line to the interconnection line. A region of the interconnection line in which the internal interconnection line is disposed is equally divided, and an area between the divided regions is removed.