3D Semiconductor Devices with TSV Interconnects and Oxide Bonding
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and limited flexibility, particularly in constructing commercially viable logic families with diverse products, and they struggle with reducing inter-chip interconnects which dominate IC performance and power consumption.
Innovation Solution
The development of a 3D IC technology using Through-Silicon-Via (TSV) connections and a modular approach with configurable logic dies, memory dies, and analog dies connected via TSVs, allowing for the construction of various systems with reduced interconnect size and increased connectivity, and the use of antifuse layers for power management and interconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If current semiconductor fabrication methods are used, then manufacturing process is established, but mask-set costs are high and flexibility is limited
Solution Approach 1:
The patent segments the semiconductor fabrication process into modular components: separate logic dies, memory dies, and analog dies that can be independently manufactured and then interconnected through TSVs. This segmentation allows different logic families to be produced using separate dies without requiring complete retooling of mask sets, thereby reducing costs while maintaining flexibility.
Solution Approach 2:
The patent transitions from planar 2D interconnection to 3D vertical interconnection using Through-Silicon-Vias (TSVs). This dimensional change enables multiple logic families and functional blocks to be stacked vertically, allowing diverse product configurations without increasing lateral mask complexity, thus reducing mask-set costs while enhancing design flexibility.
2Productivity
If traditional IC interconnection methods are used, then connections are established, but interconnect size is large and dominates IC performance and power consumption
Solution Approach 1:
The patent employs vertical Through-Silicon-Vias (TSVs) to create three-dimensional interconnections, replacing traditional lateral wire bonds and PCB traces. This vertical routing through the silicon substrate dramatically shortens interconnect lengths, reducing signal propagation delays and power consumption while improving overall IC performance.
Solution Approach 2:
The patent implements nested interconnection structures where TSVs are embedded within the silicon substrate, and multiple interconnection layers are stacked vertically. This nesting approach allows dense routing of signals and power between stacked dies, minimizing interconnect length and maximizing space utilization, thereby improving performance while reducing power consumption.
3Adaptability or versatility
If fewer TSVs are used, then manufacturing is simpler, but connectivity and interconnection capability are reduced
Solution Approach 1:
The patent segments the interconnection function across multiple TSV layers and multiple dies, where each TSV layer handles specific signaling functions. This segmentation allows the system to achieve high interconnection capability through coordinated use of multiple simpler TSV structures, rather than requiring a single complex TSV fabrication process.
Solution Approach 2:
The patent designs TSV structures that serve multiple functions: signal transmission, power distribution, and thermal management. By making TSVs multi-functional, the patent reduces the need for separate dedicated structures, thereby achieving high interconnection capability without proportionally increasing fabrication complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs by minimizing the need for multiple mask sets, enhances flexibility in producing diverse logic families, and significantly reduces interconnect size, thereby improving IC performance and power efficiency by enabling more connections in a smaller area.
Implementation Method 1
wherein the second level is bonded to the first level, wherein the bonded comprises oxide to oxide bonds
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second transistors each include at least two side-gates, and where through the first metal layers power is provided to at least one of the second transistors.