TSV Bonding Interface Recesses for Annealing Delamination Control
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Solution Overview
Problem
The expansion of metal features during annealing in stacked die and wafer bonding can lead to localized delamination due to mismatched coefficients of thermal expansion, particularly when through-silicon vias (TSVs) are involved.
Innovation Solution
Exposing and recessing the end of the TSV at the bonding surface to accommodate metal expansion, and using the TSV as a bonding contact surface, or modifying the backside of the substrate with stress-relief layers to manage thermal expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal features are used at bonding surfaces for electrical connection, then electrical conductivity is improved, but thermal expansion mismatch causes delamination during annealing
Solution Approach 1:
The patent applies preliminary action by recessing the metal features below the bonding surface before the bonding process. This pre-positioning creates a buffer zone that anticipates and accommodates the thermal expansion of metal during annealing, preventing delamination while maintaining electrical connectivity. The recess depth is specifically designed to match the expected expansion magnitude.
Solution Approach 2:
The patent implements beforehand cushioning by creating a recessed space around metal features that serves as a cushion zone. This pre-prepared space absorbs the thermal expansion stress during annealing, cushioning against the harmful effects of expansion mismatch. The cushion zone prevents the metal from pushing against and delaminating the bonding interface.
2Ease of manufacture
If through-silicon vias are exposed at bonding surface for direct bonding, then bonding process is simplified, but metal expansion causes localized delamination
Solution Approach 1:
The patent applies local quality by creating localized recesses only at the metal feature locations rather than planarizing the entire surface. This selective local modification maintains the simplified direct bonding approach while addressing the expansion issue only where needed. The surrounding dielectric surface remains flat, preserving manufacturing precision in non-critical areas.
Solution Approach 2:
The patent changes the geometric parameter of the metal features by recessing them below the surface level. This parameter modification (changing from flush-mounted to recessed) fundamentally alters how the metal interacts with thermal expansion, allowing the bonding process to remain simple while preventing delamination through the created space.
3Reliability
If metal features are recessed to accommodate expansion, then delamination is prevented, but additional processing steps are required
Solution Approach 1:
The patent merges the recess formation step with the existing bonding preparation process. Instead of adding a completely separate complex process, the recessing is integrated into the standard surface preparation or patterning steps already present in the manufacturing flow. This combination approach maintains reliability while minimizing the increase in overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces or eliminates delamination and ensures reliable bonding by providing space for metal expansion and managing thermal stress, maintaining mechanical and electrical continuity.
Implementation Method 1
the metal of the features expands afterwards, as the metal is heated during annealing. The expansion of the metal can cause the metal from both bonding surfaces to join into a unified conductive structure
Implementation Method 2
an exposed end of the conductive via is used as a bonding contact surface for direct metal-to-metal bonding without an intervening material
Data Source
AI summary
Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a through-silicon via (TSV) may be disposed through at least one of the microelectronic substrates. The TSV is exposed at the bonding interface of the substrate and functions as a contact surface for direct bonding.