TSV Interface Circuit Voltage Biasing for Parasitic Capacitance Reduction
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Solution Overview
Problem
Conventional through-substrate via (TSV) interface circuits in 3D integrated circuits (3D-ICs) suffer from high parasitic capacitance due to operating supply voltages that are equal to or higher than the interposer substrate voltage, leading to increased latency in signal transmission.
Innovation Solution
The TSV interface circuit employs lower supply voltages, specifically Vdd=−N*VDD and Vss=−(N+1)*VDD, where N is a positive integer, for the driving and receiver circuits, which are biased to be lower than the interposer substrate voltage, reducing parasitic capacitance by approximately 30%.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional supply voltages (equal to or higher than interposer substrate voltage) are used for TSV interface circuits, then the circuits can operate reliably, but parasitic capacitance increases leading to higher power consumption and lower speed
Solution Approach 1:
The patent changes the voltage parameter of the TSV interface circuit by applying a negative bias voltage (Vbias) to the interposer substrate, shifting the substrate voltage to a negative level. This parameter change allows the use of lower supply voltages (Vdd and Vss) for the interface circuit while maintaining reliable operation, thereby reducing parasitic capacitance and power consumption.
2Reliability
If conventional supply voltages are used for TSV interface circuits, then the circuits can operate reliably, but signal transmission latency increases
Solution Approach 1:
The patent applies a negative bias voltage to the interposer substrate, changing the voltage parameter to enable lower supply voltages for the TSV interface circuit. This reduction in supply voltage decreases parasitic capacitance, which in turn reduces signal transmission latency while maintaining circuit reliability.
3Use of energy by moving object
If lower supply voltages are used for TSV interface circuits, then parasitic capacitance is reduced by 30%, but the circuit requires negative bias voltage configuration
Solution Approach 1:
The patent introduces a negative bias voltage (Vbias) as an intermediary parameter applied to the interposer substrate. This intermediary voltage configuration enables the TSV interface circuit to operate with lower supply voltages and reduced parasitic capacitance, while the bias voltage mechanism manages the complexity of the voltage system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach lowers parasitic capacitance by 30%, resulting in reduced power consumption and increased speed, allowing for faster operation under the same power and voltage conditions.
Implementation Method 1
It is desirable to keep the parasitic capacitance introduced by TSV as low as possible for low latency signal transmission
Data Source
AI summary
A TSV interface circuit for a TSV provided in an interposer substrate that forms a connection between a first die and a second die includes a driving circuit provided in the first die and a receiver circuit provided in the second die where the driving circuit is coupled to a first supply voltage and a second supply voltage that are both lower than the interposer substrate voltage that substantially reduces the parasitic capacitance of the TSV. The receiver circuit is also coupled to the first supply voltage and the second supply voltage that are both lower than the interposer substrate voltage.