Through Silicon Via Interposer for 3D Semiconductor Package

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Solution Overview

Problem

Current semiconductor packaging technologies face challenges in accommodating modern 3D interconnection designs, leading to increased package size, thickness, and reduced density, which hinders the integration of advanced semiconductor chips and increases costs.

Innovation Solution

The implementation of a semiconductor package system that includes a top package with a through silicon via interposer and a bottom package with a substrate interposer, where the top package is attached to the bottom package through a center active face connection, reducing the need for peripheral solder ball interconnections and utilizing a through silicon via interposer for enhanced interconnectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If edge connection on laminated substrate is used to connect stacked chips, then routing between chips is achieved, but package length and width increase, decreasing device density

Engineering Contradiction:

Improverouting capabilityVSAvoidpackage footprint

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent transitions from 2D edge connection routing to 3D vertical routing through through-silicon-via (TSV) interposer technology. The TSV interposer enables electrical connections to pass through the substrate vertically, allowing chips to be stacked and connected in the thickness direction rather than requiring peripheral edge connections, thus reducing package footprint while maintaining routing capability

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The TSV interposer serves as an intermediary layer between stacked chips, providing through-substrate vias that enable vertical electrical interconnection. This mediator structure allows signals to traverse through the substrate thickness rather than routing along the edges, solving the routing problem while minimizing the horizontal package area

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If laminated substrate is used for 3D package interconnection, then chip stacking is enabled, but pitch capability is limited and package thickness increases

Engineering Contradiction:

Improve3D interconnection capabilityVSAvoidpackage thickness

Core Design Contradiction:

Adaptability or versatilityVSLength of stationary object

Solution Approach 1:

The patent changes the interconnection parameter from lateral edge routing to vertical through-substrate routing. By implementing TSV structures that penetrate the substrate thickness, the design achieves finer pitch capability and reduced overall package thickness compared to conventional laminated substrate edge connections

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS8063475B2Semiconductor package system with through silicon via interposer

Publication Date: 2011.11.22 STATS CHIPPAC MANAGEMENT PTE LTD

AI summary

A semiconductor package system includes: providing a top package, a through silicon via interposer embedded in the top package; providing a bottom package having a bottom semiconductor die with a top connection adjacent the center active face thereof, a substrate interposer being embedded in the bottom package, the bottom semiconductor die being attached to the substrate interposer; and attaching the top package to the bottom package, the top package having the through silicon via interposer having a via connected to the top connection.