TSV Interposer Package Using Dummy Dies for Alignment
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Solution Overview
Problem
The manufacturing of semiconductor devices with through-silicon vias (TSVs) is challenging due to alignment issues caused by component warpage, leading to increased costs and reduced yield, as conventional TSVs can only be tested after the semiconductor die is mounted to the package.
Innovation Solution
A method involving the use of dummy dies with pre-fabricated TSVs, which are integrated into a semiconductor device package before final assembly, allowing for the formation of electrical connections between semiconductor dies and enabling the creation of 3D interposer packages with simplified manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional TSVs are used and formed after die mounting, then electrical connections between semiconductor dies are achieved, but alignment precision deteriorates due to component warpage and manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming TSVs in dummy dies before mounting the semiconductor dies to the package. This allows TSVs to be created when the substrate is still relatively flat and accessible, avoiding alignment issues caused by warpage that occurs after die stacking. The TSVs are prepared in advance in sacrificial dummy structures, enabling precise formation before the actual dies are mounted and interconnected.
2Reliability
If conventional TSV testing is performed after die mounting, then electrical connections are verified, but manufacturing yield decreases and cost increases due to inability to rework
Solution Approach 1:
The patent uses dummy dies as intermediary structures that contain TSVs for testing purposes. These dummy dies serve as sacrificial test vehicles, allowing TSV functionality to be verified before final die assembly. If TSVs are defective, the dummy dies can be replaced without affecting the mounted semiconductor dies, thereby maintaining high manufacturing yield and reducing costs.
3Device complexity
If TSVs are formed after die mounting, then electrical interconnections are established, but device complexity increases and manufacturing cost increases
Solution Approach 1:
The patent segments the manufacturing process into distinct phases: (1) forming TSVs in dummy dies on the package substrate before die mounting, (2) mounting semiconductor dies to the prepared substrate, and (3) removing dummy dies. This segmentation allows TSV formation to be performed under optimal conditions on a flat substrate, simplifying the overall manufacturing process and reducing complexity compared to forming TSVs through already-mounted die stacks.
4Ease of manufacture
If dummy dies with TSVs are used before final assembly, then manufacturing process is simplified and yield improves, but device complexity increases due to additional components
Solution Approach 1:
The patent applies the discarding principle by using dummy dies as temporary, sacrificial structures that are removed after serving their purpose. The dummy dies contain TSVs that are tested and utilized during assembly, then discarded after the actual semiconductor dies are mounted and interconnected. This approach adds temporary complexity that is later removed, simplifying the final product while enabling easier manufacturing during the process.
Data Source
AI summary
A semiconductor device has a carrier for supporting the semiconductor device. A first semiconductor die is mounted over the carrier. A first dummy die having a first through-silicon via (TSV) is mounted over the carrier. The first semiconductor die and the first dummy die are encapsulated using a wafer molding material. The carrier is removed. A first redistribution layer (RDL) is formed over a first surface of the first semiconductor die and a first surface of the first dummy die to electrically connect the first TSV and a contact pad of the first semiconductor die. An insulation layer is formed over the first RDL. A second RDL is formed over a second surface of the first dummy die opposite the first surface of the first dummy die and electrically connected to the first TSV. A semiconductor package is connected to the second RDL.