TSV Interposer Stacked Semiconductor Package Design
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Solution Overview
Problem
Current semiconductor packages face challenges in miniaturization and high integration due to limitations in interposer design and manufacturing processes, particularly in efficiently connecting multiple semiconductor chips within a single package while maintaining performance and reducing size.
Innovation Solution
The semiconductor package design incorporates a lower semiconductor package with an interposer featuring through substrate vias (TSVs) and package connecting members, allowing for the stacking and electrical connection of upper semiconductor packages, which are manufactured using a method involving interposer wafers, TSV formation, and precise molding to reduce size and enhance integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional semiconductor package designs are used, then manufacturing processes are simpler, but miniaturization and high integration are limited
Solution Approach 1:
The package is divided into multiple functional layers: lower base substrate, interposer with TSVs, lower semiconductor chip, upper semiconductor package, and package connecting members. This segmentation allows each component to be optimized independently for miniaturization while maintaining overall simplicity in manufacturing
Solution Approach 2:
An interposer with through substrate vias (TSVs) is introduced as an intermediary component between the lower base substrate and semiconductor chips. This interposer enables high-density electrical connections and facilitates miniaturization by providing a compact routing structure, while the standardized TSV fabrication process keeps manufacturing complexity manageable
2Productivity
If multiple semiconductor chips are integrated into a single package, then high integration is achieved, but manufacturing complexity increases
Solution Approach 1:
The interposer is prepared in advance with TSVs formed through the substrate before chip mounting. Package connecting members are also pre-attached to the interposer. This preliminary preparation enables high integration of multiple chips without proportionally increasing manufacturing complexity, as the complex interconnection structure is established once and reused
Solution Approach 2:
The interposer serves multiple functions: providing electrical connections between chips, enabling signal routing, facilitating thermal management, and supporting the stacked package structure. This multi-functionality allows high integration of multiple chips without requiring separate specialized components for each function, thereby controlling manufacturing complexity
3Reliability
If interposer with TSVs is used, then electrical connectivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The TSV structure utilizes controlled parameter changes during fabrication: copper deposition forms conductive pathways, selective etching creates precise via holes, and metallization layers are deposited at controlled thicknesses. These parameter changes enable reliable electrical connectivity through the interposer while maintaining manufacturing precision within standard semiconductor fabrication capabilities
Data Source
AI summary
A semiconductor package having a reduced size by including an interposer having through substrate vias (TSVs), the semiconductor package may comprise a lower semiconductor package which includes a lower base substrate, an interposer with TSVs on the lower base substrate, and a lower semiconductor chip on the interposer and electrically connected to the interposer. The semiconductor package may include an upper semiconductor package on the lower semiconductor package including an upper semiconductor chip and package connecting members on the interposer and electrically connect the upper semiconductor package to the interposer. An exterior molding member may be provided.