Stacked Semiconductor TSV Alignment for Lower I/O Loading
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Solution Overview
Problem
Conventional semiconductor stacking methods are inefficient in terms of power and cost, as they often overlook power efficiency concerns and rely heavily on signal redistribution layers and wire-bond resources for electrical access.
Innovation Solution
The use of through-silicon-vias (TSVs) in stacked semiconductor devices, where the TSVs are designed and aligned to reduce input/output (I/O) loading by staggering I/O circuits and offsetting adjacent devices, allowing for optimal point-to-point connections and improved power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional stacking methods using signal redistribution layers and wire-bond resources are used, then electrical access to devices is provided, but power efficiency deteriorates and cost increases
Solution Approach 1:
The patent extracts and eliminates the power-inefficient signal redistribution layers and wire-bond resources from the stacking architecture. By removing these intermediate components and directly connecting devices through vertically aligned TSVs, the solution achieves electrical access while improving power efficiency.
Solution Approach 2:
The patent transitions from horizontal signal routing through redistribution layers to vertical signal routing through TSVs. This dimensional change in signal path orientation eliminates the need for complex lateral interconnect structures and reduces power consumption.
2Reliability
If conventional stacking methods using signal redistribution layers are used, then electrical access is achieved, but manufacturing cost increases
Solution Approach 1:
The patent removes the expensive signal redistribution layers from the manufacturing process. By using TSVs that extend through the substrate without requiring additional redistribution layers, the solution reduces manufacturing complexity and cost while maintaining electrical access functionality.
Solution Approach 2:
The TSV structure serves multiple functions: it provides mechanical support, enables electrical connection, and eliminates the need for separate signal redistribution layers. This multi-functionality reduces the total number of manufacturing steps and materials required.
3Ease of manufacture
If TSVs are aligned without staggering I/O circuits, then device alignment is simplified, but I/O loading on via paths increases reducing system speed
Solution Approach 1:
The patent introduces asymmetric offsetting between the TSV array and the I/O circuit array. By deliberately misaligning these two arrays, the design reduces the capacitive loading effect on TSV paths while maintaining manufacturable alignment tolerances through the use of alignment marks and compensation techniques.
Solution Approach 2:
The patent applies different alignment strategies to different regions of the device. The TSV array and I/O circuit array are offset from each other, creating local variations in the electrical connection geometry that reduce I/O loading on critical signal paths while maintaining overall structural integrity.
4Adaptability or versatility
If more I/O circuits are coupled to each via path, then connectivity is increased, but power efficiency decreases and system speed reduces
Solution Approach 1:
The patent segments the I/O circuits into separate arrays that are offset from the TSV array. This segmentation allows each TSV to connect to fewer I/O circuits, reducing the capacitive loading and power consumption while maintaining overall system connectivity through the distributed array structure.
Data Source
AI summary
A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies.