TSV Keep Out Zone Reduces BEOL Pumping Stress
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Solution Overview
Problem
The deformation of through silicon vias (TSVs) due to stress buildup from coefficient of thermal expansion differences between copper and semiconductor materials, known as 'pumping,' causes stress-induced voiding and dishing in integrated circuit structures, particularly at smaller technology nodes, which existing approaches like annealing or offsetting vias cannot consistently control.
Innovation Solution
Positioning zero layer vias laterally within the upper surface area of TSVs and placing subsequent interconnect layers' vias outside a defined keep out zone over the TSVs to reduce stress transmission and deformation, while maintaining minimal resistance increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If zero vias are placed over the center of TSV, then electrical connectivity is maintained, but stress-induced voiding and deformation increase
Solution Approach 1:
The patent applies local quality by creating a spatially varying via distribution pattern: zero vias are concentrated at the center of TSV to maintain electrical connectivity, while subsequent interconnect vias are positioned outside a keep-out zone to reduce stress. This non-uniform spatial distribution optimizes both connectivity and stress management in different regions.
Solution Approach 2:
The patent segments the via placement into distinct zones: a central region with zero vias for connectivity, a keep-out zone for stress reduction, and peripheral regions for subsequent interconnects. This segmentation allows independent optimization of each zone's function.
2Object-affected harmful factors
If TSV size is reduced to lower copper volume, then pumping stress is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the geometric parameters of TSV and via placement (sizes, positions, keep-out zone dimensions) to optimize the balance between stress reduction and manufacturing feasibility. These parameter adjustments allow stress management without requiring extreme precision.
3Object-affected harmful factors
If via placement is offset from TSV center, then stress-induced voiding is reduced, but electrical resistance increases
Solution Approach 1:
The patent maintains high via density at the TSV center where electrical connectivity is critical, while offsetting subsequent interconnect vias from the center where stress management is critical. This local differentiation resolves the contradiction between connectivity and stress reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces stress-induced voiding and dishing, maintaining the integrity of dielectric layers and interconnects with only a negligible increase in resistance, even at advanced technology nodes.
Implementation Method 1
pumping is a phenomenon in which end surfaces of TSVs deform due to stresses created by the large differences in coefficient of thermal expansion (CTEs) between the copper and the surrounding semiconductor materials
Data Source
AI summary
An IC structure and related method are provided. The IC structure includes: a semiconductor substrate and a TSV disposed within the semiconductor substrate. A first interconnect layer includes a plurality of V0 vias disposed on the TSV, where the plurality of V0 vias are positioned laterally within an upper surface area of the TSV. At least one second interconnect layer disposed over the first interconnect layer includes a plurality of vias laterally positioned outside of a keep out zone positioned over the TSV. The method includes forming a first interconnect layer including a plurality of V0 vias disposed on a TSV, the V0 vias positioned laterally within an upper surface area of the TSV, and forming at least one second interconnect layer disposed over the first interconnect layer and including a plurality of vias laterally positioned outside of a keep out zone positioned over the TSV.